FIFO Logic Circuit Timing Using Input and Output Ring Counters
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Solution Overview
Problem
Traditional flip-flop chain architectures in memory devices are inefficient in performing combination logic operations due to time wastage in each flip-flop stage and inability to utilize available clock cycles effectively, leading to either multiple stages being performed in a single clock cycle or unused cycles during result transfer.
Innovation Solution
A FIFO stack circuit with a combination logic circuit that uses an input ring counter and output ring counter circuit to manage data flow and timing, allowing for high-speed combination logic operations across the entire available number of clock periods without the inefficiencies of previous architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chained flip-flop architecture is used to perform combination logic operations, then the logic operations can be performed in stages, but time is wasted in each flip-flop stage due to setup time and data delivery delay
Solution Approach 1:
The combination logic is divided into multiple independent pipeline stages, each stage processing a portion of the logic operation. Data flows through multiple flip-flops in sequence, with each flip-flop stage handling a specific segment of the overall logic function. This segmentation allows the total logic operation to be distributed across multiple clock cycles, reducing the complexity and delay of individual stages.
Solution Approach 2:
The system uses periodic clocking to advance data through the pipeline stages. Each clock cycle triggers the next stage of processing, creating a rhythmic flow of data through the combination logic. This periodic action synchronizes the multi-stage processing and allows predictable timing analysis of the overall operation.
2Reliability
If parity latency is set to match the number of logic stages, then calculation can be completed within the latency period, but additional clock periods cannot be utilized effectively
Solution Approach 1:
The system dynamically adapts the pipeline depth and stage configuration based on the available latency budget. When additional clock periods are available, the system can increase the number of pipeline stages or reduce the complexity of individual stages to better utilize the available time, thereby improving throughput without compromising calculation completion.
3Duration of action of moving object
If multiple logic stages are performed in a single clock cycle to meet parity latency, then the calculation completes within the latency period, but the complexity and timing constraints of each stage increase
Solution Approach 1:
The combination logic is divided into multiple independent pipeline stages, each stage processing a portion of the logic operation. Data flows through multiple flip-flops in sequence, with each flip-flop stage handling a specific segment of the overall logic function. This segmentation allows the total logic operation to be distributed across multiple clock cycles, reducing the complexity and delay of individual stages.
Data Source
AI summary
Apparatuses for performing combination logic operations with a combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.