FIFO Memory Management Circuit for Constant-Time Allocation
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Solution Overview
Problem
The time complexity of memory management operations increases with the growth of memory size due to the complexity of managing separated and irregular storage spaces in low-latency storage devices, particularly in systems with multiple computing engines sharing the memory.
Innovation Solution
A memory management circuit with a controller and address mapping logic that records available storage space addresses in a FIFO storage device, generating a mapping table based on a specific order to allow efficient allocation of storage resources without increasing time complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separated empty spaces in low-latency storage device are searched and put together by establishing a mapping table, then computing engines can utilize storage spaces with continuous addresses, but time complexity of memory management increases in response to growth of memory size
Solution Approach 1:
The patent segments the memory management task by separating the recording of available storage space addresses from the generation of mapping tables. The FIFO storage device stores first addresses of available storage spaces, while the controller generates mapping tables only when storage requests are received, dividing the complex management into manageable segments that reduce overall time complexity
Solution Approach 2:
The patent applies preliminary action by pre-recording the first addresses of available storage spaces in the FIFO storage device before storage requests arrive. This preliminary recording allows the controller to quickly generate mapping tables when needed, rather than searching for available spaces at the moment of request, thus reducing time complexity while maintaining allocation efficiency
Data Source
AI summary
A memory management circuit, an electronic device and a memory management method are provided. The memory management circuit includes a controller and an address mapping logic. The controller records addresses of available storage spaces within a memory device, wherein a searching logic of the controller stores the addresses in a storage device, and the addresses are queued with a specific order in the storage device. When a computing circuit send a storage request to request for a storage resource, the searching logic obtains at least one address queued in the storage device according to the specific order of the addresses queued in the storage device, to accordingly generate a mapping table, and the address mapping logic performs an address mapping operation upon the storage request according to the mapping table, to allow the computing circuit to utilize the available storage spaces according to the mapping table.