FIFO Memory Balancing for Deadlock Avoidance in Multi-Processor Architectures
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Solution Overview
Problem
Multi-processor computing architectures are vulnerable to deadlocks, which cause permanent cessation of data processing, due to imbalances in pipeline depths and mismatches in producer-consumer write-read rates.
Innovation Solution
A method that involves compiling a design for a data processing array, simulating it using a modified device model with infinite FIFO memory models, and determining FIFO memory requirements to alleviate deadlocks by inserting additional FIFO memory on specific nets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data streams are processed through multi-processor architectures with pipeline stages, then computational capabilities and data throughput are increased, but pipeline depth imbalances cause deadlocks that permanently cease data processing
Solution Approach 1:
The patent applies preliminary action by simulating the design before implementation using a modified device model with infinite FIFO memory. This simulation phase allows detection of pipeline depth imbalances and calculation of required FIFO memory sizes before the actual design is compiled and implemented, preventing deadlocks from occurring in the first place
Solution Approach 2:
The patent introduces an intermediary mechanism - the modified device model with infinite FIFO memory - that acts as a mediator between design compilation and final implementation. This intermediary simulation environment allows analysis of data flow patterns and calculation of FIFO requirements without the constraints of actual hardware resource limits
2Reliability
If FIFO memory is added to data paths to balance pipeline depths, then deadlocks are avoided and data processing continues, but device complexity and resource requirements increase
Solution Approach 1:
The patent applies local quality by calculating and adding FIFO memory only to specific data paths where pipeline depth imbalances exist, rather than uniformly adding memory throughout the entire system. The simulation identifies exact locations and quantities of FIFO memory needed, minimizing overall device complexity while achieving deadlock avoidance
Solution Approach 2:
The patent changes the parameter of FIFO memory depth from a fixed or uniform value to a dynamically calculated value based on simulation results. By analyzing data flow patterns in the modified device model, the system determines optimal FIFO depths for each data path, balancing reliability improvement with minimal resource consumption
3Measurement precision
If simulation uses infinite FIFO memory models, then accurate FIFO requirements can be determined, but the modified device model deviates from actual hardware constraints
Solution Approach 1:
The patent segments the device modeling process into two distinct phases: first, simulation using a modified device model with infinite FIFO memory to accurately measure data flow patterns and calculate requirements; second, implementation using the actual device model with finite FIFO resources. This segmentation allows each phase to use the most appropriate model for its purpose
Data Source
AI summary
Providing first-in-first-out (FIFO) memory guidance for a multi-processor computing architecture includes compiling a design for a data processing array to generate a compiled design. The compiled design is mapped and routed to the data processing array. The compiled design is simulated using a modified device model of the data processing array. The modified device model uses infinite FIFO models. FIFO memory usage data is generated by tracking amounts of data stored in the infinite FIFO memory models during runtime of the simulation of the compiled design. FIFO memory requirements for one or more nets of the design are determined from the FIFO memory usage data and the compiled design.