FIFO Memory Channel for Low-Latency Inter-Process Communication
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Solution Overview
Problem
Current shared memory computing systems face latency issues and security vulnerabilities due to software-managed communication between processes, which can lead to inefficiencies and potential side channel attacks.
Innovation Solution
Implementing a method to enable FIFO-like communication between distributed processes using a memory channel that exploits locality in the cache hierarchy and communication buses, allowing for low-latency, high-throughput message passing while maintaining security through hardware-based solutions, and allowing the OS to create memory regions that behave like FIFO devices without relying on physical memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-managed shared memory communication is used between processes, then security can be guaranteed through OS management, but communication latency increases due to multiple hardware agent interactions
Solution Approach 1:
The patent introduces a dedicated communication channel with its own address space that acts as an intermediary between sender and receiver processes. This channel includes a buffer region and control region that mediate data transfer, eliminating the need for processes to directly share memory while maintaining secure OS-managed communication. The channel abstraction layer resolves the contradiction by providing both security (through OS management) and low latency (through direct channel-based transfer without general shared memory overhead).
Solution Approach 2:
The patent segments the communication mechanism into distinct components: a dedicated channel structure with separate buffer region and control region, isolated from general shared memory. This segmentation allows the communication subsystem to operate independently with optimized pathways, reducing latency while maintaining security through structured access control. The channel is divided into functional parts that can be managed separately by the OS.
2Productivity
If shared memory regions are used for data transfer, then communication can be implemented, but security vulnerabilities arise due to side channel attacks exploiting cache hierarchy associativity
Solution Approach 1:
The dedicated communication channel acts as an intermediary that prevents direct exploitation of cache associativity between unrelated processes. By routing all communication through a structured channel with controlled access, the patent eliminates the side channel vulnerability while maintaining productivity. The channel's buffer and control regions are accessed through defined protocols that prevent unauthorized cache-based information leakage.
Solution Approach 2:
The patent applies local quality by creating a specialized communication channel with distinct memory regions (buffer and control) that have specific access characteristics. This localized structure ensures that data transfer occurs through controlled pathways with predictable cache behavior, preventing side channel attacks while maintaining efficient data movement. The channel region has different access properties than general shared memory, providing security through localized access control.
3Productivity
If multiple hardware agents interact to pass data through shared memory, then data can be transferred between processes, but device complexity increases
Solution Approach 1:
The dedicated communication channel serves as a simplified intermediary structure that reduces hardware agent coordination complexity. Instead of multiple agents managing general shared memory access, the channel provides a dedicated pathway with built-in buffer and control mechanisms. This intermediary structure absorbs the coordination complexity internally while presenting a simple interface to processes, maintaining productivity without requiring complex multi-agent interaction.
Data Source
AI summary
A system, apparatus and method for enabling a FIFO-like (first-in-first-out) communication between a plurality of executing processes that are distributed throughout a computing system. Embodiments exploit locality in the hierarchy of the cache memory and communication busses within the computing system to enable the passing of messages or streams of bytes with a low latency and high throughput. In addition, this allows for participating components to be very simple, or very sophisticated, but still benefit from the improved communications patterns.