FIFO Memory Error Circuit Using Pointer Overlap Detection
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Solution Overview
Problem
Existing FIFO memory error detection circuits require a large number of logic gates and circuit area to detect overrun and underrun conditions, with previous solutions like gray code sequences and extra status bits being inefficient in terms of resources.
Innovation Solution
A FIFO memory error circuit with read and write pointer control logic, where the read and write pointers are set to logic high outputs for specific numbers of clock cycles, and an error is detected when these outputs overlap, utilizing an AND gate and latch to generate an error signal with minimal gate requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gray code sequence is used for error detection, then error detection capability is improved, but the number of logic gates and circuit area increase significantly
Solution Approach 1:
The patent extracts only the essential comparison function from the full gray code sequence, using a simplified approach where only the most significant bit comparison is performed to detect errors, thereby reducing the number of logic gates while maintaining detection capability
Solution Approach 2:
The patent applies partial action by checking only a subset of pointer states (specifically when read pointer equals write pointer or read pointer equals write pointer plus one) rather than monitoring all possible states, which reduces circuit complexity while still detecting the critical error conditions
2Reliability
If extra status bits are added to each FIFO location, then error detection accuracy is improved, but circuit area and implementation complexity increase
Solution Approach 1:
The patent makes the pointer comparison circuit multi-functional by using the same read and write pointer signals to detect both overrun and underrun conditions, eliminating the need for separate status bits for each location and reducing overall circuit area
Solution Approach 2:
The patent merges the error detection function into the existing pointer control logic by using the read and write pointer signals directly in the comparison circuit, rather than adding separate status bit storage and comparison circuits for each FIFO location
Data Source
AI summary
A FIFO memory error circuit has a read pointer coupled to a FIFO memory. The read pointer has a logic high output once every FIFO memory cycle. A write pointer is coupled to the FIFO memory and has a logic high output once every FIFO memory cycle. An error detector has a first input coupled to the read pointer and a second input coupled to the write pointer.