FIFO Memory Error Detection Without Cycle Interruption
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Solution Overview
Problem
Existing error detection systems for memories, such as FIFO memories, interrupt write cycles when comparing write and read signatures, leading to delays in data packet storage due to the requirement for the FIFO memory to be empty.
Innovation Solution
An error detection system that includes a write signature generation circuit, a read signature generation circuit, a trigger generation circuit, and synchronization and comparison circuits, allowing for error detection without halting write cycles by using a trigger signal to latch and compare signatures at predefined intervals, enabling continuous operation even when the FIFO memory is not empty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the error detection system compares write and read signatures only when the FIFO memory is empty, then error detection accuracy is improved, but write cycles are interrupted causing productivity loss
Solution Approach 1:
The system latches the write signature and write address in advance when a trigger signal occurs, before the FIFO memory becomes empty. This preliminary action allows the comparison to be performed later without interrupting the write cycle, as the latched values are preserved for subsequent comparison when the read address catches up to the write address.
2Measurement precision
If the FIFO memory halts write cycles to compare signatures, then measurement precision of errors is improved, but loss of time increases
Solution Approach 1:
The latching circuit acts as an intermediary that stores the write signature and write address temporarily. This intermediary mechanism allows the comparison operation to be decoupled from the write cycle, enabling continuous writing while the latched values are compared later without causing time loss in the write operation.
3Productivity
If continuous error detection is implemented without halting cycles, then productivity is improved, but device complexity increases due to additional latching and trigger circuits
Solution Approach 1:
The latching circuit serves multiple functions: it stores the write signature for error detection, holds the write address for comparison, and enables continuous operation. The trigger generation circuit also provides multi-functionality by initiating the latching process and coordinating the error detection timing. This multi-functionality reduces the need for separate dedicated circuits for each function.
Data Source
AI summary
An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. A write signature generation circuit generates a write signature of a second data packet. When a trigger generation circuit generates a trigger signal, a first latching circuit stores a write address as a latch write address and a second latch stores the write signature as a latch write signature. A first synchronization and comparison circuit generates a comparison signal based on the latched write address and a read address. A second synchronization and comparison circuit generates a fault signal based on the comparison signal, the latched write signature, and the read signature.