On-board FIFO Memory Module for High-Speed DUT Testing
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Solution Overview
Problem
Current very low cost test systems (VLCT) for integrated circuits are limited by their clock speed, leading to inefficiencies and increased costs due to the need to operate at lower speeds, which causes synchronization issues and slows down production.
Innovation Solution
A test module that interposes between the tester and the device under test, capable of communicating at both the tester and device clock speeds, using a memory module to store and transfer samples at selectable clock speeds, thereby decoupling time synchronization and enabling at-speed testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If VLCT systems operate at their maximum clock speed to improve testing speed, then productivity increases, but the system cannot test high-speed devices with clock rates exceeding 30 MHz
Solution Approach 1:
A test module is introduced as an intermediary component between the VLCT system and the high-speed device under test. This test module includes a FIFO memory that can operate at both the VLCT clock speed (30 MHz) and the device clock speed (greater than 30 MHz), acting as a speed-matching bridge that enables communication between systems with different clock rates
Solution Approach 2:
The system dynamically changes the operating clock speed parameter of the test module based on the device being tested. The test module can switch between operating at the VLCT clock speed (30 MHz) when interfacing with the tester, and at the device clock speed (greater than 30 MHz) when interfacing with the high-speed device, thereby adapting to different testing requirements
2Reliability
If VLCT systems operate at lower clock speeds to maintain synchronization, then compatibility is maintained, but test time increases and productivity decreases
Solution Approach 1:
The FIFO memory in the test module serves as a buffer that decouples the timing requirements between the VLCT system and the high-speed device. It allows the VLCT to operate at its fixed 30 MHz clock speed while the device operates at its native higher clock speed, with the FIFO absorbing the timing differences and preventing synchronization issues
Solution Approach 2:
The system performs preliminary speed matching by having the test module operate at the device's clock speed to capture data, then transfers the captured data to the VLCT at the VLCT's clock speed. This preliminary high-speed capture followed by controlled transfer prevents data loss while maintaining overall system synchronization
3Speed
If conventional ATE systems are used to achieve high-speed testing capability, then testing performance improves, but system cost and complexity increase significantly
Solution Approach 1:
The high-speed testing capability is segmented into a separate, modular test module that can be added to the existing VLCT system. Rather than requiring a complete high-speed ATE system, only the essential FIFO memory and control logic are added, keeping the overall system complexity low while achieving the desired speed capability
Solution Approach 2:
The patent uses a cost-effective approach by implementing the FIFO memory with simple, readily available components rather than expensive proprietary high-speed memory. The test module is designed to be a simple add-on that provides high-speed capability without the million-dollar price tag of conventional ATE systems
Data Source
AI summary
In a method and system for testing, a tester (110) is operable to communicate test signals (124, 126) at a tester clock speed, and a device (190) to be tested is operable to communicate the test signals (124, 126) at a device clock speed, the device clock speed being greater than the tester clock speed. A test module (120) is interposed between the tester (110) and the device (190) to enable data transfer between the tester (110) and the device (190) at their respective clock speeds. The test module (120) includes a memory module (250) capable of storing N samples of the test signals (124, 126) at a selectable one of the tester clock speed and the device clock speed. The memory module (250) is operable to provide the N samples at a selectable one of the tester clock speed and the device clock speed.