FIFO Memory Multi-Port Functionality Area Reduction
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Solution Overview
Problem
Conventional FIFO memories, including dual-port and multi-port versions, face challenges such as increased area requirements and limited simultaneous read and write capabilities, making them inefficient for asynchronous operations and requiring a more compact solution with enhanced functionality.
Innovation Solution
A FIFO memory architecture utilizing multiple single-port memory structures with an indexing block and access controller to manage operations, allowing for multi-port functionality while minimizing area usage by dynamically allocating write and read operations across available single-port memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual-port FIFO memory is used to enable simultaneous read and write operations, then multi-port functionality is achieved, but the area occupied increases to almost double that of a single-port memory
Solution Approach 1:
The patent divides the multi-port memory system into multiple single-port memory structures, each handling specific operations. Instead of using one large dual-port memory, the system segments functionality across multiple smaller single-port memories with an indexing block that routes operations to the appropriate memory structure, thereby achieving multi-port functionality without the area penalty of a single large dual-port memory.
2Adaptability or versatility
If conventional multi-port FIFO memory is used to provide multiple write operations and single read operation, then multi-port functionality is achieved, but the size becomes much bigger compared to single-port or dual-port memories
Solution Approach 1:
The patent makes single-port memory structures universal by enabling them to perform multiple functions through the indexing block and access controller. The same single-port memory structure can be dynamically allocated for different operations (read, write, or both) based on the indexing block contents, allowing conventional single-port memories to provide multi-port functionality without requiring specialized multi-port memory structures.
3Area of stationary object
If single-port memory is used to reduce area, then area efficiency is improved, but the ability to perform simultaneous read and write operations is limited
Solution Approach 1:
The patent introduces an indexing block as an intermediary between the control logic and multiple single-port memory structures. This indexing block stores information about which memory structure should be accessed for each operation, enabling the system to coordinate simultaneous read and write operations across multiple single-port memories without requiring them to be physically integrated into a single dual-port structure, thus maintaining area efficiency while improving operational capability.
Data Source
AI summary
A memory may require a buffering mechanism in which data can be written and read at the same time. This requires a multi-port FIFO memory, which has multiple ports, thus providing simultaneous read & write operations. Multi-port memories have a large penalty on area. Hence, a technique is proposed for avoiding use of multi-port memories for designs which requires sequential read and write operations. In this technique multiple single-port memories are used to form a multi-port memory. This memory requires additional control logic but consumes significantly lower silicon area.