Reconfigurable FIFO Memory with Programmable Queue Depth
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Solution Overview
Problem
Conventional first-in-first-out (FIFO) memory devices have limited configurability, with a fixed number of queues and depths, restricting their ability to interrelate data flows and operate efficiently in complex data processing scenarios.
Innovation Solution
A flexible FIFO memory device with programmable configurations that allow interrelated queues, where input and output queues can be merged, split, or operate through arithmetic/logic functions, enabling a variable number of queues and depths, and allowing for different queue sizes and rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FIFO memory devices use a fixed number of queues with small fixed values (4-8), then the device structure is simple and easy to manufacture, but the adaptability and versatility are limited for complex data processing scenarios
Solution Approach 1:
The patent implements dynamic configurability where the number of queues and their depths can be programmed at runtime. The FIFO device transitions from a static fixed-queue structure to a dynamic reconfigurable structure, allowing the system to adapt queue configurations based on specific data processing requirements while maintaining a unified memory architecture underneath.
Solution Approach 2:
The patent creates a universal FIFO memory device that can function as multiple different queue configurations. A single physical memory array can be dynamically partitioned into different numbers of queues with different depths, making the device universally applicable to various data processing scenarios without requiring multiple dedicated hardware structures.
2Productivity
If conventional FIFO memory devices have each queue with the same fixed depth, then the manufacturing process is simplified, but the ability to optimize for different data rates and processing needs is reduced
Solution Approach 1:
The patent enables different queues to have different depths (local quality) while using a unified memory structure. Each queue can be configured with the optimal depth for its specific data processing requirements, allowing some queues to be deeper for high-rate data streams while others remain shallow for lower-rate streams, optimizing overall system productivity.
Solution Approach 2:
The patent implements programmable control over queue parameters including number of queues, depth of each queue, and inter-queue relationships. Configuration registers allow dynamic adjustment of these parameters to match different data processing scenarios, enabling optimization of data rates and processing efficiency without changing the physical hardware structure.
3Loss of energy
If conventional FIFO memory devices operate with independent queues, then the control logic is simpler, but the ability to interrelate data flows and reduce bandwidth requirements is limited
Solution Approach 1:
The patent enables merging of multiple input queues into fewer output queues, allowing data from multiple sources to be consolidated. This reduces the total bandwidth required for data processing by eliminating redundant memory access operations and allows efficient implementation of data compression and aggregation functions.
Solution Approach 2:
The patent introduces programmable control logic that acts as an intermediary between queues, enabling arithmetic and logic operations between data from different queues. This mediator layer allows complex data flow interrelationships while maintaining efficient memory access patterns and reducing overall bandwidth requirements through intelligent data processing.
Data Source
AI summary
A first-in-first-out (FIFO) memory device may include a plurality of memory locations configurable into M input queues comprising sequences of input data values and N output queues for storing sequences of output data values, wherein N is not equal to M.