FIFO Memory Dynamic Resizing via Shadow Pointers
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Solution Overview
Problem
Existing hardware implementations of FIFO memory buffers face inefficiencies when resizing, as they often require cumbersome and inefficient mechanisms like reallocation or data copying, leading to potential data loss or disruption during size changes.
Innovation Solution
A state machine with additional pointers 'new_base' and 'new_top' allows for dynamic resizing of FIFO memory by shifting existing pointers within unoccupied regions, enabling enlargement or shrinkage without data loss or operational disruption, and allowing real-time data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the FIFO buffer size is increased to accommodate more data elements, then the data storage capacity is improved, but the device complexity and memory resource usage increase
Solution Approach 1:
The patent implements dynamic buffer resizing by introducing shadow pointers (new_base, new_top) that allow the FIFO buffer size to be adjusted during runtime. The state machine monitors buffer occupancy and automatically triggers resizing operations when thresholds are reached, transforming the static buffer into a dynamic structure that adapts to varying data requirements without manual intervention.
Solution Approach 2:
The patent changes the parameter of buffer size from a fixed constant to a variable that can be modified during operation. By using shadow pointers to define new buffer boundaries and implementing a state machine that manages the transition between old and new boundaries, the system enables flexible parameter adjustment while maintaining continuous operation.
2Reliability
If data copying mechanisms are implemented to preserve data during buffer resizing, then data loss is prevented, but the operation time and processing overhead increase
Solution Approach 1:
The patent extracts the resizing operation from the critical data path by using shadow pointers that define new buffer boundaries independently of the current data. The state machine manages the transition by selectively enabling write operations to new regions and read operations from valid regions, avoiding the need to copy or migrate existing data during the transition.
Solution Approach 2:
The patent performs preliminary allocation of shadow buffer regions before they are needed. The shadow pointers (new_base, new_top) predefine the boundaries of future buffer regions, and the state machine prepares the transition by validating that the new region is properly allocated and ready to receive data, eliminating the need for runtime data copying.
3Adaptability or versatility
If the FIFO buffer is enlarged during operation to meet increasing data requirements, then adaptability is improved, but the device complexity and control mechanisms increase
Solution Approach 1:
The patent implements self-service buffer management through an automatic state machine that monitors buffer occupancy levels and triggers resizing operations autonomously. The state machine evaluates current buffer status, determines when resizing is needed based on predefined thresholds, and executes the transition using shadow pointers without requiring external control logic or manual intervention, thereby simplifying the overall control architecture.
4Productivity
If pointer shifting is implemented to modify the allocated memory region, then buffer resizing efficiency is improved, but the risk of pointer errors and data loss increases
Solution Approach 1:
The patent introduces shadow pointers (new_base, new_top) as intermediaries between the control logic and the actual buffer boundaries. These shadow pointers serve as a safe abstraction layer that allows the state machine to plan and validate buffer transitions without directly manipulating the active pointers. The intermediary shadow pointers enable efficient resizing while maintaining reliability through validated transition sequences.
Data Source
AI summary
A FIFO memory having a modifiable memory region; the FIFO memory being configured as a linear memory and as a circular buffer; the FIFO memory having a state machine that contains a new base value and a new top value for definition of a memory region allocated in the future, the lower boundary of which region is defined by the new base value and the upper boundary of which is defined by the new top value, and the state machine is configured in such a way that in a read mode and/or a write mode of the FIFO memory, the allocated memory region of the FIFO memory is modifiable by shifting the base pointer to the new base value, and/or by shifting the top pointer to the new top value.