Network Flow Reordering with FIFO Queues for Parallel Processing
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Solution Overview
Problem
In Ethernet-based communication networks, packet reordering becomes complex and resource-intensive, especially in parallel processing environments, leading to performance degradation due to out-of-order packet delivery, particularly in multicast scenarios.
Innovation Solution
A network traffic transfer system utilizing a combination of FIFO memory circuits and processing engines, along with a controller, ensures packet ordering by designating specific processing engines for unicast and multicast traffic, and employs reordering engines to maintain the original packet order through control signals and FIFO memory pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel processing environments with multiple processing threads are used to increase throughput, then network throughput is improved, but packet reordering complexity and device complexity increase significantly
Solution Approach 1:
The patent divides packet processing into separate segments: processing engines handle packet processing independently while reordering engines handle packet reordering. Each processing engine has dedicated FIFO queues for different packet types (unicast, multicast, mirrored), and reordering engines are assigned specific packet streams to reorder. This segmentation allows parallel processing to maintain throughput while distributing reordering complexity across multiple specialized components rather than requiring complex coordination logic.
2Reliability
If single processing thread is used to guarantee packet ordering, then packet order is maintained, but network throughput is limited
Solution Approach 1:
The patent introduces FIFO queues as intermediary structures between processing engines and output interfaces. These queues act as buffers that temporarily hold packets from multiple processing threads, allowing packets to be processed in parallel while maintaining first-in-first-out ordering within each queue. The reordering engines then retrieve packets from these intermediary queues in the correct sequence, enabling both parallel processing and ordered delivery without requiring a single processing thread.
3Adaptability or versatility
If reordering logic is implemented in software, then flexibility is maintained, but processing speed and throughput are reduced
Solution Approach 1:
The patent replaces software-based reordering logic with dedicated hardware reordering engine circuits implemented in ASIC. These hardware circuits use parallel comparators, priority encoders, and FIFO memory structures to perform reordering operations at line rate speeds. The hardware implementation maintains the flexibility needed for different packet types and reordering scenarios while achieving processing speeds that software cannot match, thereby resolving the trade-off between adaptability and processing speed.
Data Source
AI summary
Various embodiments provide systems and methods for reordering processed network traffic.