FIFO Overflow Prevention in Reconfigurable Processor Data Scheduling
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Solution Overview
Problem
In coarse-grained reconfigurable processor architectures, data overflow and loss occur due to dynamic changes in flow depth, leading to inefficiencies in data processing and throughput, as existing FIFO management methods fail to effectively handle the varying cache space requirements.
Innovation Solution
A data scheduling system with a first and second FIFO, along with write and read pointer control components, determines the empty and full states of the FIFOs to prevent overflow and ensure correct data transmission by incrementally updating cache addresses and triggering control signals to manage data flow effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the reconfigurable array dynamically adjusts the flow depth to meet different application requirements, then the computing flexibility and adaptability are improved, but data overflow and loss occur in the FIFO buffer
Solution Approach 1:
The patent applies preliminary action by pre-configuring the FIFO buffer with a predetermined capacity and establishing advance control mechanisms before data overflow can occur. The control unit monitors buffer status in advance and adjusts data transmission accordingly, preventing overflow rather than reacting after it occurs. This resolves the contradiction by enabling dynamic flow depth adjustment while maintaining data integrity through proactive buffer management.
Solution Approach 2:
The patent implements feedback through a control unit that continuously monitors the FIFO buffer's fill status and uses this information to regulate data transmission between the reconfigurable array and memory. When the buffer approaches capacity, the control unit reduces or pauses data transmission, creating a closed-loop system that maintains data integrity while allowing flexible flow depth configuration. This feedback mechanism resolves the contradiction by dynamically adapting data flow to buffer capacity constraints.
2Reliability
If the FIFO buffer capacity is increased to prevent data overflow, then data integrity is improved, but the overall system memory consumption increases
Solution Approach 1:
The patent applies partial action by configuring the FIFO buffer with a predetermined capacity that is sufficient for typical operation but not excessively large. The control unit manages data transmission to utilize this limited buffer capacity efficiently, avoiding the need for oversized buffer allocation. This partial buffering approach maintains data integrity for practical workloads while minimizing overall memory consumption, resolving the contradiction between data integrity and memory usage.
3Productivity
If the reconfigurable array processes data with dynamic flow depth changes, then computing performance is improved, but data loss occurs due to insufficient cache space
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a control unit that mediates between the reconfigurable array's dynamic processing needs and the limited FIFO buffer capacity. This intermediary monitors buffer status and regulates data flow, acting as a buffer manager that prevents data loss while allowing the reconfigurable array to operate at optimal performance levels with varying flow depths. The control unit serves as the mediator that resolves the contradiction between computing performance and data loss prevention.
Data Source
AI summary
Disclosed in the present invention are a data scheduling system, when data to be processed is transmitted from the first FIFO to a reconfigurable array, the first write pointer control component allocates a first write cache address; when the reconfigurable array writes a processing result into the second FIFO, the second write pointer control component allocates a second write cache address; when the processing result cached in the second FIFO is read by a system bus, the read pointer control component allocates a read cache address; the empty-state determination control component determines an empty-state of the second FIFO according to the second write cache address and the read cache address; and the full-state determination control component determines a full-state of the second FIFO according to the first write cache address and the read cache address.