Data Link Layer Device FIFO Buffer Packet Assembly
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Solution Overview
Problem
In point-to-point protocols, achieving a balance between transmission efficiency and delay is challenging due to varying data lengths, as longer packets reduce auxiliary information but increase processing time, leading to limitations in data link layer encapsulation.
Innovation Solution
A data link layer device with first-in first-out (FIFO) modules that accumulate and reformat data to create continuous, longer packets, reducing unnecessary transmissions and improving efficiency by synchronizing data transfer with available buffer space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the length of link layer packet is increased to reduce auxiliary information transmission, then transmission efficiency is improved, but processing delay increases due to limited data processing capacity per clock cycle
Solution Approach 1:
The patent applies preliminary action by pre-accumulating data in the first FIFO buffer before packetization. The data accumulation unit continuously stores incoming data segments in the first FIFO, preparing them in advance for future packet assembly. This allows the system to quickly form long packets when buffer space becomes available, without requiring real-time data collection, thus reducing processing delay while maintaining high transmission efficiency
Solution Approach 2:
The patent introduces an intermediary mechanism through the two-FIFO buffer structure. The first FIFO acts as an intermediary between data sources and the packet assembly process, while the second FIFO serves as an intermediary between assembled packets and the transmission interface. This intermediary buffer system decouples data accumulation from packet transmission, allowing independent optimization of both processes to resolve the contradiction between packet length and processing delay
2Loss of time
If multiple small data segments are transmitted separately, then processing delay is reduced, but transmission efficiency decreases due to increased auxiliary information
Solution Approach 1:
The patent applies merging by combining multiple small data segments accumulated in the first FIFO into a single long packet before transmission. The data assembly unit continuously merges available data segments, filling the packet to the preset maximum length. This merging process reduces the total number of packets required, thereby reducing the overhead of auxiliary information such as headers and check codes, and improving overall transmission efficiency without significantly increasing processing delay
3Loss of substance
If data is accumulated to form long packets, then auxiliary information transmission is reduced, but buffer management complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the buffer management function into two independent FIFO structures with distinct responsibilities. The first FIFO is dedicated to raw data accumulation with simple write operations, while the second FIFO handles assembled packets with simple read operations. This segmentation eliminates the need for complex buffer management algorithms, as each FIFO operates independently with straightforward first-in-first-out semantics, reducing management complexity while still enabling long packet formation
Data Source
AI summary
A data link layer device and a packet encapsulation method are provided. The data link layer device includes a first and a second first-in-first-out (FIFO) module. The first FIFO module receives and stores multiple first data from an upper-layer module, and removes data gaps from the first data to store the first data in a continuous form. When the first FIFO module is not empty, the first FIFO module generates data of different lengths based on the current amount of data stored temporarily in the first FIFO module and a preset data length. When the data queue of the second FIFO module has enough space to receive the first data, the first FIFO module transfers the first data to the second FIFO module, and the first FIFO module transfers a header including the data length to a header queue of the second FIFO module.