FIFO Pointer Synchronization Across Switching Clock Domains
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Solution Overview
Problem
Existing data processing systems face significant latency issues when switching between different clock synchronization mechanisms across clock domains, particularly when adjusting clock frequencies to match processing loads, as current methods require draining FIFO memories and stopping data transmission, leading to prolonged processing cycles.
Innovation Solution
The implementation of a first-in-first-out (FIFO) memory circuitry with a pointer synchronizing circuit that dynamically changes synchronization paths by holding pre-switch pointer values in a transition register until post-switch values are synchronized, allowing continuous data flow and reducing latency during mode transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronisation mechanisms are used to pass pointers across clock domain boundaries, then glitch and meta-stability resistance is achieved, but latency increases
Solution Approach 1:
The synchronisation mechanism dynamically adjusts its behaviour based on the relationship between first and second clock signals. When clocks are synchronous, pointers are passed directly without synchronisation delays. When clocks are asynchronous or at different frequencies, the mechanism activates appropriate synchronisation paths with D-type latches, reducing unnecessary latency while maintaining reliability when needed.
Solution Approach 2:
The system changes the synchronisation parameters (path selection, latch activation) based on clock relationship parameters. The control logic monitors clock frequency and synchronisation status, adjusting the pointer passing mechanism accordingly - using direct passing when clocks match, and synchronised passing when they differ, thus optimizing the balance between latency and reliability.
2Productivity
If clock frequency scaling is implemented to match processing load, then energy efficiency and performance matching improve, but synchronisation complexity increases
Solution Approach 1:
The pointer synchronisation circuit is designed to handle multiple clock relationship scenarios using the same hardware structure. It can manage synchronous clocks, asynchronous clocks, and frequency-scaled clocks through a unified mechanism that automatically detects the clock relationship and applies appropriate synchronisation, avoiding the need for separate mechanisms for each scenario.
Solution Approach 2:
The synchronisation mechanism dynamically adapts to changing clock frequencies and relationships during operation. When clock frequencies are scaled to match processing load, the control logic detects the frequency relationship and automatically adjusts the pointer passing strategy, enabling flexible frequency scaling without requiring complex manual reconfiguration or multiple dedicated synchronisation paths.
3Reliability
If FIFO draining is performed during clock mechanism switching, then pointer synchronisation stability is maintained, but processing time increases significantly
Solution Approach 1:
The control logic prepares for clock mechanism switches by pre-assessing the clock relationship and pre-selecting the appropriate synchronisation path. This preliminary assessment allows the system to execute switches more quickly without requiring conservative FIFO draining, as the control mechanism is already prepared to handle the transition appropriately based on pre-evaluated clock conditions.
Solution Approach 2:
The system continuously monitors the relationship between first and second clock signals and uses this feedback to dynamically adjust pointer passing behaviour. During clock mechanism switching, the feedback mechanism detects changes in clock frequency or synchronisation status and automatically adjusts the pointer synchronisation strategy, allowing faster switches without FIFO draining while maintaining stability through continuous adaptation.
4Adaptability or versatility
If multiple synchronisation mechanisms are provided for different clock relationships, then adaptability improves, but switching between mechanisms becomes difficult
Solution Approach 1:
Multiple synchronisation mechanisms are merged into a single unified control structure. The control logic integrates synchronous passing, asynchronous synchronisation with D-type latches, and frequency-scaled synchronisation into one cohesive system that automatically selects and executes the appropriate path based on real-time clock relationship detection, eliminating the need for separate switchable modules.
Solution Approach 2:
The unified control mechanism dynamically selects and activates the appropriate synchronisation path based on the detected clock relationship. Rather than requiring manual or complex automated switching between separate mechanisms, the dynamic control logic continuously monitors clock frequencies and synchronisation status, automatically adjusting the pointer passing behaviour to match the current clock relationship, thereby achieving adaptability with simplified switching.
Data Source
AI summary
An integrated circuit 2 is provided with multiple clock domains separated by a clock boundary 8. Data values are passed across the clock boundary 8 using a first-in-first-out memory (FIFO), a read pointer and a write pointer for the FIFO are passed across the clock boundary 8 and must be synchronized to the receiving clock frequency. The clocks being used on either side of the clock boundary 8 may be switched and have a variable relationship therebetween. Multiple synchronization paths are provided within pointer synchronizing circuitry 32 which are used depending upon the particular relationship between the clocks on either side of the clock boundary 8. A pre-switch pointer value is held in a transition register 44 until a post-switch pointer value is available from the new synchronizing path 36 when a switch in clock mode is made which requires an increase in synchronization delay.