FIFO Circuit Power Optimization via Consecutive Data Detection
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Solution Overview
Problem
Existing FIFO circuits in electronic devices consume excessive power due to unnecessary switching activities, especially when dealing with consecutive identical data entries, which is not efficiently managed by current memory and logic configurations.
Innovation Solution
A FIFO circuit design that includes a memory block and a logic circuit, where the logic circuit compares input data with previous data to detect consecutive identical entries, and suppresses operations in selected memory cells when the number exceeds a threshold, using a gated clock signal or masked enable signals to reduce power consumption by minimizing switching activities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If memory cells continuously operate to store every incoming data entry, then FIFO buffering function is maintained, but power consumption increases due to unnecessary switching activities on identical consecutive data
Solution Approach 1:
The patent applies partial action by selectively suppressing memory cell operations only when consecutive identical data entries are detected, rather than continuously operating all memory cells. The logic circuit monitors data sequences and gates clock signals or masks enable signals to prevent unnecessary write operations, reducing power consumption while maintaining FIFO functionality for valid data transitions.
Solution Approach 2:
The patent implements feedback through a logic circuit that continuously compares current input data with previously stored data, detects consecutive identical entries, and generates control signals (clock gating or enable masking) accordingly. This feedback mechanism ensures the FIFO circuit adapts its operation based on the actual data pattern, suppressing power-consuming operations only when redundancy is detected.
2Use of energy by stationary object
If logic circuit continuously compares and controls each data entry, then power optimization is achieved, but device complexity increases
Solution Approach 1:
The patent segments the power optimization function into a separate logic circuit module that works independently from the main memory array. The logic circuit is divided into data comparison units and control signal generation units, allowing modular implementation that adds minimal complexity while achieving power savings. This segmentation enables the complex comparison and control functions to be isolated from the core FIFO operation.
3Use of energy by stationary object
If clock signal is gated to suppress memory operations, then power consumption reduces, but switching activity in logic circuit increases
Solution Approach 1:
The patent extracts the power-consuming clock signal generation from the memory block and places the clock gating logic in a separate control circuit. By taking out the clock distribution function and controlling it externally based on data comparison results, the memory block itself consumes less power during idle periods, while the extracted control logic manages the switching activity separately, allowing for more efficient power management of the overall system.
Data Source
AI summary
Aspects of the disclosure provide a first-in-first-out (FIFO) circuit having a memory block and a logic circuit. The memory block includes an array of memory cells configured to be able to store N data entries in a FIFO order (N is a positive integer). The logic circuit is configured to compare input data with previously input data to detect a number of consecutive identical entries of input data, and suppress an operation of selected memory cells when the number is larger than N.