Power Domain Crossing FIFO Data Integrity Verification

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Solution Overview

Problem

Modern computing systems with multiple power domains face challenges in maintaining data integrity during power domain crossings, particularly in high-performance applications where user safety is critical, such as advanced driver assistance systems (ADAS).

Innovation Solution

The method involves selecting a memory location in a first power domain, calculating a first error check value, transferring the data through level shifters, calculating a second error check value in the destination power domain, and comparing the two values to detect data corruption during transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If power domain crossing is implemented to enable power-saving techniques, then power efficiency is improved, but data integrity deteriorates

Engineering Contradiction:
Improvepower efficiencyVSAvoiddata integrity
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by calculating and transferring the first error check value from the source power domain before data transmission occurs. This pre-computed error check value is then used at the destination to immediately detect any corruption, enabling proactive protection of data integrity while maintaining power efficiency benefits.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The error check value acts as an intermediary element that mediates between the source and destination power domains. By transferring this computational checksum alongside the data through the power domain boundary, the system enables verification of data integrity without requiring continuous power consumption in intermediate verification stages.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If conventional data transfer methods are used across power domains, then device complexity is reduced, but detection time of data corruption increases to milliseconds

Engineering Contradiction:
Improvesystem complexityVSAvoiddetection time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent reduces detection time by performing the error check calculation in advance at the source power domain. The pre-computed first error check value is transferred with the data, allowing the destination domain to immediately compare values and detect corruption within nanoseconds rather than performing lengthy verification computations after data arrival.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If error check values are calculated and compared across power domains, then data integrity detection is improved to nanosecond level, but device complexity increases

Engineering Contradiction:
Improvedata integrity detectionVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the error checking function into two separate power domains. The source power domain calculates and transfers the first error check value, while the destination power domain calculates and compares the second error check value. This segmentation allows each domain to perform simplified, specialized operations rather than requiring one domain to handle the entire complex verification process.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12314214B2Ensuring data integrity in power domain crossing FIFO queues
Publication Date: 2025.05.27 QUALCOMM INC
  • US12314214B2 patent drawing
  • US12314214B2 patent drawing
  • US12314214B2 patent drawing

AI summary

Aspects of the present disclosure provide techniques and apparatus for transferring data, such as between power domains via a first in, first out (FIFO) queue. An example method of transferring data includes selecting, via a source multiplexer, a first memory location included in a FIFO queue and storing first data, where the source multiplexer and the FIFO queue are in a first power domain; outputting the first data to a first level shifter; calculating, in the first power domain, a first value based on the first data; outputting the first value to a second level shifter; selecting, via at least one destination multiplexer included in a second power domain, the first level shifter and the second level shifter; calculating, in the second power domain, a second value based on the first data; and comparing the first value to the second value to generate a result.