FIFO Buffer Reset Mechanism for EMI-Resilient Image Processing
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Solution Overview
Problem
Conventional image processing systems face operational errors and abnormal display issues due to electromagnetic interference (EMI) when using a phase-lock loop (PLL) clock generator designed for CRT monitors with LCD displays, leading to overflow phenomena in FIFO buffers.
Innovation Solution
An image processing device and method that includes a reset signal generator to opportunistically reset the FIFO buffer indices when specific conditions are met, such as the end of a frame or scan line, ensuring the data writing and reading indices are aligned, thereby minimizing overflow errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a spread spectrum clock signal is used to reduce EMI emission in LCD displays, then electromagnetic interference is reduced, but frequency difference between clock signals causes operational errors and overflow in FIFO buffer
Solution Approach 1:
The patent implements a feedback mechanism by monitoring the frequency difference between the spread spectrum clock signal and the original clock signal, and dynamically adjusting the FIFO buffer operation or generating compensation signals to maintain synchronized data reading and writing, thereby preventing overflow while preserving EMI reduction benefits
Solution Approach 2:
The patent changes the operating parameters of the FIFO buffer by dynamically adjusting the data reading speed or buffer depth based on the actual frequency deviation of the spread spectrum clock signal, ensuring reliable operation under varying frequency conditions while maintaining EMI reduction
2Object-affected harmful factors
If the frequency of spread spectrum clock signal varies with time to disperse the clock signal spectrum, then EMI emission is reduced, but overflow phenomenon occurs in FIFO buffer
Solution Approach 1:
The patent applies preliminary action by pre-calculating and compensating for the expected frequency variation of the spread spectrum clock signal before it causes overflow, using pre-established synchronization mechanisms or predictive algorithms to adjust FIFO operations in advance, thereby preventing overflow while maintaining EMI reduction
Solution Approach 2:
The patent implements beforehand cushioning by increasing the FIFO buffer depth or creating a larger data buffer margin to accommodate the frequency variations of the spread spectrum clock signal, providing a cushion zone that prevents overflow while preserving the EMI reduction benefits of spread spectrum modulation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents operational errors and ensures normal display operations by aligning FIFO buffer indices, reducing the likelihood of overflow and maintaining stable image processing across different display types.
Implementation Method 1
the SSC generator 20 spreads the frequency spectrum of the clock signal LCDCLK to generate a spread spectrum clock signal SSCLK
Data Source
AI summary
An image processing device includes a frame buffer, a first display engine, a clock signal generator, a spread spectrum clock generator, a first-in-first-out (FIFO) buffer and a reset signal generator. The FIFO buffer receives and stores the pixel digital data from the first display engine according to a data writing index controlled by a working clock signal from the clock signal generator and outputs the pixel digital data to the planar display according to a data reading index controlled by a spread spectrum clock signal from the spread spectrum clock generator. The reset signal generator receives and checks the pixel digital data and generates a reset signal to the FIFO buffer to reset the data writing index and the data reading index when one of the pixel digital data to be inputted into the FIFO buffer is consistent with a preset condition.