Data FIFO Circuit Segmented Multiplexing for DDR4 Signal Overload
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Solution Overview
Problem
Conventional FIFO circuits face challenges in high-speed data-rate applications, particularly in DDR4 SDRAMs, due to increased circuit complexity and signal overload, which affects reliability and compactness.
Innovation Solution
A data FIFO circuit design incorporating a register unit with decoders and multiple data multiplexers, along with an output multiplexer, to facilitate sequential data output and reduce circuit complexity, mitigating signal overload through a two-stage multiplexing approach.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a larger number of registers and multiplexers are used to meet higher CAS latency requirements in DDR4 SDRAM, then the data transfer capability is improved, but the circuit complexity increases
Solution Approach 1:
The patent divides the large multiplexer into multiple smaller multiplexers (first plurality and second plurality of multiplexers, each being 4-to-1). The register unit is also segmented into multiple registers (N registers where N≥4). This segmentation reduces the complexity of individual multiplexer components while maintaining the overall data transfer capability through parallel operation of multiple smaller units.
Solution Approach 2:
The patent introduces a hierarchical structure with two levels of multiplexing: first multiplexers select data from registers, and second multiplexers select from the outputs of first multiplexers. This dimensional organization transforms a flat complex selection problem into a structured two-stage process, reducing control signal complexity while maintaining high data transfer capability.
2Adaptability or versatility
If more control signals are used to control a larger number of multiplexers, then the data routing flexibility is improved, but the number of trace lines increases
Solution Approach 1:
The control function is segmented across multiple multiplexer stages. Each 4-to-1 multiplexer requires only 2 control signals, and by organizing multiple such multiplexers in hierarchical stages, the total control signal count is reduced compared to a single large multiplexer. The segmented control approach maintains routing flexibility through coordinated operation of multiple smaller control units.
Solution Approach 2:
Instead of using a single large multiplexer that would require many control signals, the patent employs multiple smaller multiplexers that collectively provide equivalent or excessive selection capability. This partial action approach uses multiple 4-to-1 multiplexers to achieve the functionality of a larger multiplexer with fewer control signals per unit, reducing the overall trace line burden.
3Device complexity
If a single large multiplexer is used to handle all data outputs, then the circuit structure is simplified, but signal overload occurs
Solution Approach 1:
The patent divides the single large multiplexer function into multiple smaller multiplexers operating in parallel stages. The first plurality of multiplexers handles initial data selection from registers, and the second plurality handles subsequent selection. This segmentation distributes the signal load across multiple components, preventing signal overload while maintaining a relatively simple hierarchical circuit structure.
Solution Approach 2:
The patent introduces a hierarchical dimension to the multiplexer structure, organizing multiplexers into multiple stages rather than using a single flat structure. This dimensional organization allows data to flow through multiple smaller multiplexer stages, distributing the signal processing load and preventing overload on any single component while maintaining overall structural simplicity.
Data Source
AI summary
A data first-in first-out (FIFO) circuit includes a register unit, a plurality of data multiplexers, and an output multiplexer. The register unit includes a plurality of decoders and a plurality of N registers. The decoders are used for outputting a plurality of decoded signals in response to a plurality of corresponding input control signals and at least one input enabling signal. The N registers are configured to receive input data in response to the corresponding decoded signals from the corresponding decoders. The data multiplexers each are coupled to M ones of the registers, wherein N and M are positive integers, N is equal to or greater than four, M is equal to or greater than two, and N is greater than M. The output multiplexer, coupled to the data multiplexers, is used for providing a corresponding output from the data multiplexers sequentially.