FIFO Store Queue with Checkpoint-Based Aggressive Merging
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Solution Overview
Problem
Modern processors face challenges with store queues due to the high semiconductor area and power consumption requirements of content addressable memory (CAM) circuits, which limit the number of entries and cause delays in committing stores to the memory hierarchy.
Innovation Solution
A processor design that uses a first-in-first-out (FIFO) store queue with checkpointing mechanisms, allowing for limited merging of stores before a checkpoint, aggressive merging after a checkpoint, and efficient management of commit and merge pointers to optimize store queue operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CAM circuits are used to compare store queue entries with load addresses, then store forwarding can be determined, but semiconductor area and power consumption increase significantly
Solution Approach 1:
The patent extracts the address comparison function from the CAM circuit and implements it using simpler comparison logic in the store queue entry structure. Each store entry includes the address and a generation counter, allowing comparisons to be made through straightforward logic rather than complex CAM circuitry.
Solution Approach 2:
The patent replaces the expensive CAM circuit with a simpler, more economical store queue entry structure that uses basic comparators and counters. This cheaper structure achieves the same functional outcome (determining store forwarding) without the high area and power costs of CAM circuits.
2Productivity
If CAM circuits are used to compare store queue entries with load addresses, then store forwarding can be determined, but power consumption increases significantly
Solution Approach 1:
The patent extracts the address comparison function from the CAM circuit and implements it using simpler comparison logic in the store queue entry structure. Each store entry includes the address and a generation counter, allowing comparisons to be made through straightforward logic rather than complex CAM circuitry.
Solution Approach 2:
The patent replaces the expensive CAM circuit with a simpler, more economical store queue entry structure that uses basic comparators and counters. This cheaper structure achieves the same functional outcome (determining store forwarding) without the high area and power costs of CAM circuits.
3Productivity
If CAM circuits are used to compare store queue entries with load addresses, then store forwarding can be determined, but processor design complexity increases
Solution Approach 1:
The patent extracts the address comparison function from the CAM circuit and implements it using simpler comparison logic in the store queue entry structure. Each store entry includes the address and a generation counter, allowing comparisons to be made through straightforward logic rather than complex CAM circuitry.
Solution Approach 2:
The patent replaces the expensive CAM circuit with a simpler, more economical store queue entry structure that uses basic comparators and counters. This cheaper structure achieves the same functional outcome (determining store forwarding) without the high area and power costs of CAM circuits.
4Quantity of substance
If the number of store queue entries is increased, then more stores can be buffered, but CAM circuit size must increase which worsens area and power consumption
Solution Approach 1:
The patent extracts the address comparison function from the CAM circuit and implements it using simpler comparison logic in the store queue entry structure. Each store entry includes the address and a generation counter, allowing comparisons to be made through straightforward logic rather than complex CAM circuitry.
Solution Approach 2:
The patent replaces the expensive CAM circuit with a simpler, more economical store queue entry structure that uses basic comparators and counters. This cheaper structure achieves the same functional outcome (determining store forwarding) without the high area and power costs of CAM circuits.
5Quantity of substance
If stores are held in the store queue for extended periods, then store buffering is achieved, but store commit delays occur
Solution Approach 1:
The patent introduces dynamic generation counters that increment with each store entry, enabling the system to dynamically track and manage store entries. This dynamic approach allows the processor to efficiently determine when stores can be forwarded or committed, reducing delays while maintaining buffering capacity.
Solution Approach 2:
The patent changes the parameter tracking mechanism from static CAM circuit comparisons to dynamic generation counter comparisons. By using generation counters that increment with each store, the system can dynamically manage store entries and determine commit timing more efficiently, reducing store commit delays.
Data Source
AI summary
Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.