Asynchronous FIFO Testing Circuit with Comparator
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Solution Overview
Problem
Testing asynchronous FIFOs in memory devices is challenging due to the difficulty in synchronizing and decoding asynchronous clock signals, particularly when moving the trailing edge of the EMPTY signal from the write clock domain to the read clock domain, which can lead to metastability issues and requires significant engineering effort.
Innovation Solution
A circuit and method that involves coupling a stream of data from a first clock domain to a second clock domain using a comparator circuit to ensure reliable transfer of the trailing edge of the EMPTY signal, utilizing a pair of FIFOs with separate write and read clocks, and comparing data output to the incoming stream to verify proper synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronization techniques such as synchronizing flip-flops are used to move the trailing edge of the EMPTY signal to the read clock domain, then the signal synchronization is achieved, but metastability issues are created
Solution Approach 1:
The patent uses an intermediary circuit (the testing circuit with comparator) to mediate the synchronization process. Instead of directly synchronizing the EMPTY signal using flip-flops that cause metastability, the comparator circuit indirectly handles the signal transfer by comparing data values, thereby achieving synchronization without the harmful metastability effect
Solution Approach 2:
The patent replaces the mechanical/synchronous synchronization mechanism (flip-flops) with a computational approach (comparator circuit). The comparator substitutes the traditional clock-domain crossing mechanism, achieving the same synchronization goal through data comparison rather than edge-triggered flip-flop transitions
2Measurement precision
If thorough testing of the FIFO is performed to verify clock synchronization, then testing accuracy is improved, but testing time increases significantly
Solution Approach 1:
The testing circuit performs preliminary actions by continuously monitoring and comparing data values in the background. The comparator is already in place and actively comparing data, so when a timing relationship issue occurs, the test result is immediately available without requiring lengthy verification procedures
Solution Approach 2:
The patent maintains continuous useful action through the ongoing data comparison process. The comparator continuously compares incoming data with expected values, ensuring that testing is always active and ready to detect synchronization issues without requiring periodic or extended test sequences
Data Source
AI summary
Circuit and methods for testing a memory device are disclosed. According to one aspect of the invention, a circuit for testing an asynchronous data transfer comprises a first circuit receiving a stream of data in response to a clock signal in a first clock domain. A second circuit coupled to the first circuit receives the stream of data from the first circuit in response to a low level of an empty signal in the second clock domain. A comparator circuit coupled to receives the stream of data and the output of the second circuit. Specific applications to dual port RAMs as well as implementations in a programmable logic devices are disclosed. Various methods of testing an asynchronous data transfer are also disclosed.