Figure-Eight Inductor with Nested Capacitors
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Solution Overview
Problem
Current RF inductor structures face inefficiencies in area usage due to the need for significant space to minimize electromagnetic interference, leading to a trade-off between performance and circuit size.
Innovation Solution
The implementation of a figure-eight inductor configuration with extensions from input and output nodes that allow capacitors to be disposed within the inductor loop, forming a capacitor array to electromagnetically shield the intersection portion, thereby enabling efficient use of the active area and reducing electromagnetic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a larger area is used for the inductor to maintain desirable performance, then the Q factor and performance are improved, but the circuit size increases significantly
Solution Approach 1:
The patent places circuit components (capacitors, transistors, resistors) inside the loops of the figure-eight inductor structure. The inductor loops are configured to enclose these components, allowing them to be nested within the inductor's geometric boundaries. This nesting approach enables the circuit components to occupy the space within the inductor loops, thereby improving area efficiency while maintaining the inductor's performance characteristics.
Solution Approach 2:
The patent combines the inductor structure with other circuit components by placing capacitors, transistors, and resistors within the inductor loops. The figure-eight configuration merges the inductor function with the housing function, allowing multiple components to share the same physical space. This merging reduces the overall circuit footprint while maintaining individual component performance.
2Area of stationary object
If a smaller circuit size is achieved by reducing inductor area, then the circuit footprint is reduced, but the Q factor and performance are sacrificed
Solution Approach 1:
By nesting circuit components within the inductor loops, the patent achieves a compact layout where the inductor's geometric boundaries define the space for other components. This allows the circuit to achieve a smaller overall footprint while the inductor maintains its full effective area for performance.
Solution Approach 2:
The patent utilizes the two-dimensional space within the inductor loops by placing components in different layers (metal layers) vertically above or below the inductor traces. This dimensional approach allows components to occupy the same planar projection area without interfering with the inductor's electrical performance, effectively using the third dimension (vertical stacking) to resolve the area-performance trade-off.
3Reliability
If metal-only area is used to host the inductor, then the inductor performance is optimized, but the area efficiency of the circuit is reduced
Solution Approach 1:
The figure-eight inductor structure serves multiple functions: it provides the inductive function while simultaneously serving as a housing or container for other circuit components. The loops of the figure-eight configuration create enclosed spaces that can accommodate capacitors, transistors, and resistors, making the inductor structure universal in its functionality rather than dedicated solely to inductance.
Solution Approach 2:
The patent nests capacitors, transistors, and resistors within the loops of the figure-eight inductor. This nesting allows the inductor to perform its electrical function while the enclosed space is utilized by other components, thereby improving area efficiency without compromising inductor performance.
4Productivity
If circuit components are placed inside the inductor loop, then area efficiency is improved, but electromagnetic interference may increase
Solution Approach 1:
The patent strategically places capacitors within the inductor loops to serve dual purposes: they function as electrical components while simultaneously acting as shielding elements. The capacitors' metal structures and connections create electromagnetic shielding that contains the inductor's magnetic field within the loops, converting what could be harmful interference into a beneficial shielding effect.
Solution Approach 2:
The capacitors placed within the inductor loops act as intermediaries that mediate the electromagnetic interaction. Their metal structures and connections create a shielding barrier that contains the magnetic field, preventing it from interfering with external components while allowing the inductor to maintain its performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances area usage by allowing electrical components to be placed within the inductor loop while minimizing electromagnetic interference, resulting in improved performance and reduced circuit size without sacrificing performance.
Implementation Method 1
the capacitor array operates to electromagnetically shield at least a part of the intersection portion
Implementation Method 2
An inductor, which usually takes a form of a coil, is an electrical component that has two terminals and stores electric energy in a magnetic field when an electric current is flowing through it
Data Source
AI summary
Embodiments described herein provide circuitry employing an inductor having enhanced circuit area usage. The circuitry includes an inductor having a first loop and a second loop adjoining the first loop to form a figure-eight configuration. The circuitry further includes a circuit component disposed at least partially inside an area defined by at least one of the first loop and the second loop. The inductor has an intersection portion between the first loop and the second loop. An input node is located proximate to the intersection portion, the input node having a first extension disposed inside the first loop. An output node is located proximate to the intersection portion. The output node has a second extension disposed inside the second loop. At least a first capacitor is coupled to the input node and the second extension, and at least a second capacitor coupled to the output node and the first extension.