Fill Structure for Straight Dicing Edges in Low-k Dielectrics

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Solution Overview

Problem

The existing methods for singulating chips with low-k or ultra-low-k dielectrics using stealth dicing often result in non-straight dicing edges, chipping, and delamination issues, which can lead to reliability problems during assembly and packaging.

Innovation Solution

Incorporating a fill structure within the dicing line of the wafer, which extends along the dicing edge of the chip, to direct the fracture propagation and reduce the risk of chipping and delamination, while maintaining a narrow dicing line width less than 100 μm or 25 μm, thereby improving the breaking behavior and chip reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If stealth dicing is used to singulate chips with low-k or ultra-low-k dielectrics, then productivity is improved by enabling parallel chip production, but the dicing edges become non-straight and chipping/delamination occurs

Engineering Contradiction:
Improveparallel chip productionVSAvoiddicing edge straightness
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A fill structure is introduced as an intermediary element within the dicing line to mediate the singulation process. This fill structure, positioned in the dicing line, guides the fracture propagation during stealth dicing, ensuring straight dicing edges while maintaining the benefits of parallel chip production on the wafer

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If stealth dicing is used for chip singulation, then additional manufacturing costs are avoided, but chipping and delamination issues occur reducing chip reliability

Engineering Contradiction:
Improvemanufacturing costVSAvoidchip reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The fill structure is prepared in advance within the dicing line before the stealth dicing process. This preliminary action of placing the fill structure guides the fracture propagation during singulation, preventing chipping and delamination issues that would otherwise reduce chip reliability, while still using the cost-effective stealth dicing method

Inventive Principle:
Principle #10Preliminary action

3Productivity

If the dicing line width is reduced to increase chip density on wafer, then productivity is improved, but the risk of chipping and delamination increases

Engineering Contradiction:
Improvechip density on waferVSAvoidchipping and delamination risk
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The fill structure serves as a mediator within the narrow dicing line, enabling the use of reduced dicing line widths to increase chip density while preventing the harmful effects of chipping and delamination. The fill structure guides fracture propagation even in confined spaces, making narrow dicing lines safe to use

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The fill structure ensures straight dicing edges and reduces the risk of chipping and delamination, enhancing the reliability of the chips, especially for those with an average half-pitch equal or smaller than 65 nm, without increasing dicing line width or additional costs.

Implementation Method 1

the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge... to direct the fracture propagation and reduce the risk of chipping and delamination

Methodology Applied
Scientific EffectFracture propagation: Fracture Mechanics

Data Source

PatentUS9040354B2Chip comprising a fill structure
Publication Date: 2015.05.26 INFINEON TECHNOLOGIES AG
  • US9040354B2 patent drawing
  • US9040354B2 patent drawing
  • US9040354B2 patent drawing

AI summary

A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.