Extending Diffusion Length via Filler Cells in Logic Placement
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Solution Overview
Problem
Conventional logic cell placement techniques struggle to effectively mitigate length-of-diffusion (LOD) effects in transistors, particularly in FinFET technologies, where extending diffusion regions to improve performance is hindered by the need for uniform Fin counts and diffusion edge sharing, leading to limitations in cell placement and potential short circuits.
Innovation Solution
The method involves replacing conventional diffusion cuts with floating gates and adding filler cells with filler diffusion regions to extend the length of diffusion nodes, ensuring they share the same potential and meet maximum length specifications, thereby improving drive strength and performance while allowing for the placement of cells with different Fin counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diffusion regions are extended to improve LOD and transistor performance, then transistor drive strength and performance improve, but cell placement flexibility deteriorates due to non-uniform Fin counts and diffusion edge sharing constraints
Solution Approach 1:
The patent introduces filler cells as intermediary elements between logic cells with different Fin counts. These filler cells contain diffusion regions that extend the diffusion length of adjacent logic cells without requiring the logic cells themselves to have uniform dimensions. The filler cells act as mediators that enable LOD improvement while maintaining placement flexibility.
Solution Approach 2:
The patent segments the diffusion region extension function into two parts: the logic cells maintain their functional diffusion regions, while separate filler cells provide the additional diffusion length. This segmentation allows each cell type to have optimized characteristics - logic cells for functionality and filler cells for diffusion extension - resolving the contradiction between performance and placement flexibility.
2Length of stationary object
If logic cells with different Fin counts are placed adjacently to enable diffusion edge sharing, then effective LOD increases, but manufacturing precision deteriorates due to varying diffusion lateral widths
Solution Approach 1:
The patent applies local quality by making the filler cells have specific properties tailored to their location and function. Each filler cell's diffusion region width is locally adjusted to match the lateral width requirements of adjacent logic cells with different Fin counts, enabling precise diffusion alignment without requiring all cells to have uniform dimensions.
Solution Approach 2:
The patent changes the diffusion region parameters (width, length) of filler cells to match adjacent logic cells. By adjusting these parameters locally for each filler cell position, the patent achieves precise diffusion alignment and extended LOD while accommodating different Fin counts in neighboring logic cells.
3Ease of manufacture
If diffusion cuts are used to bound diffusion regions in conventional logic cells, then cell boundaries are clearly defined for placement, but LOD effect worsens due to limited diffusion length
Solution Approach 1:
The patent extracts the diffusion boundary function from the logic cells themselves and places it in separate filler cells. The logic cells can now have extended diffusion regions without being constrained by diffusion cuts at their boundaries, as the boundary definition function is taken out and performed by the adjacent filler cells.
Solution Approach 2:
Filler cells serve as intermediaries that assume the boundary-defining diffusion cut function. This allows logic cells to extend their diffusion regions beyond what would be permitted by conventional boundary definitions, improving LOD while maintaining clear cell boundaries through the filler cell structure.
Data Source
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Figure 3A~3B
AI summary
Systems and methods relate to cell placement methodologies for improving length of diffusion of transistors. For example, a first transistor with a first diffusion node which is bounded by a first diffusion cut is identified in a transistor level layout. The first diffusion cut is replaced with a first floating gate, and a first filler cell with a first filler diffusion region is added to extend a length of diffusion of the first diffusion node. Increasing the length of diffusion leads to improving drive strength and performance of the first transistor.