Filler Cell Diode for Antenna Effect Charge Bleeding
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Solution Overview
Problem
Integrated circuits with thin gate oxides are susceptible to damage from electrostatic charge buildup during fabrication, particularly when transistors have gates tied to the power grid, as existing solutions require additional design steps and can introduce new design rule violations.
Innovation Solution
Incorporating a filler cell with a diode connected to the power supply rail and substrate, which bleeds away accumulated charge to the substrate during fabrication, providing protection without altering the existing chip layout or introducing additional design steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional antenna protection methods (adding diodes near transistors) are used, then gate oxide damage is prevented, but device complexity and design verification steps increase
Solution Approach 1:
The patent introduces an intermediary filler cell containing a diode that is not directly connected to the transistor gate but instead connects to the power supply rail. This intermediary structure provides charge dissipation path without requiring direct connection to the protected device, thereby preventing gate oxide damage while maintaining design simplicity and avoiding additional verification steps.
2Reliability
If existing antenna protection solutions are implemented, then charge buildup is prevented, but additional design rule verification is required
Solution Approach 1:
The filler cell is designed to automatically provide charge dissipation functionality during fabrication without requiring manual intervention or additional design verification. The diode within the filler cell self-activates when charge buildup occurs, bleeding charge to the substrate without needing external control or verification steps, thereby simplifying the manufacturing process.
3Reliability
If filler cells are added to protect against antenna effects, then gate oxide damage is reduced, but layout modifications are required
Solution Approach 1:
Instead of adding protection elements in the horizontal plane near the transistor gate (traditional approach), the patent utilizes the vertical power supply rail dimension. The filler cell connects to the power supply rail and provides charge dissipation through the substrate, effectively using a different spatial dimension to achieve protection without cluttering the transistor vicinity or requiring complex layout modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the risk of gate oxide damage by allowing charge dissipation to the substrate, avoiding the need for layout changes and subsequent design rule verification, thus simplifying the design process and reducing the risk of design complications.
Implementation Method 1
a diode connected to the power supply rail and the substrate of the integrated circuit. The diode is reverse biased during normal integrated circuit operation and bleeds charge accumulated on the power supply rail during fabrication of the integrated circuit to the substrate
Data Source
AI summary
A filler cell for use in fabricating an integrated circuit. The filler cell couples a power supply rail of an adjacent logic cell to a power supply rail of another adjacent logic cell. The filler cell also has a diode to bleed charge accumulated on the power rails of the adjacent logic cells to the substrate. The diode is reverse biased during normal integrated circuit operation. A method for fabricating an integrated circuit with a power grid. At least one filler cell is placed on the integrated circuit to bleed away charge accumulated on the power grid during the fabrication of the integrated circuit. The filler cell is connected to a supply rail of an adjacent logic cell.