Filler Cell Current Paths for Transistor Source IR Drop Reduction
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Solution Overview
Problem
Existing chip designs face challenges in reducing IR drops across conductive paths, which can degrade the performance of active devices and lead to circuit failures due to increased resistance.
Innovation Solution
The implementation of a chip structure that includes active and filler cells, where the filler cell is coupled to the source of the transistor in the active cell and a rail, providing additional current paths to reduce IR drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip designs with standard conductive paths are used, then the chip structure is simple and easy to manufacture, but IR drops increase leading to degraded active device performance
Solution Approach 1:
The chip is divided into active cells and filler cells, where each cell type has specific structures optimized for their function. The filler cells segment the overall chip structure to provide additional current paths without disrupting the active cell functionality, thereby reducing IR drops while maintaining manageable structural complexity
Solution Approach 2:
The filler cells serve multiple functions: they provide additional current paths to reduce IR drops, maintain structural regularity for manufacturing, and can be integrated into the standard chip fabrication process. This multi-functionality allows the structure to address performance issues without proportionally increasing complexity
2Reliability
If additional current paths are added to reduce IR drops, then active device performance improves, but the chip structure becomes more complex
Solution Approach 1:
The filler cells are merged with the active cells in a regular alternating pattern, and the conductive paths are combined across both cell types. This merging approach creates additional current paths while maintaining structural regularity, preventing exponential growth in complexity despite the added functionality
Solution Approach 2:
The invention introduces vertical stacking of conductive paths through multiple metal layers, utilizing the third dimension to create additional current paths. This dimensional approach allows multiple parallel conduction routes without significantly increasing the planar footprint or lateral complexity of the chip structure
Data Source
AI summary
Aspects of the present disclosure provide a filler cell that may be placed next to the active cell to reduce a current-resistor (IR) drop for the active cell. The filler cell includes an active dummy device coupled to a source of a transistor in the active cell and a rail (e.g., a ground rail or a voltage supply rail). The filler cell provides the active cell with at least one additional current path between the source of the transistor and the rail through the active dummy device, which reduces the IR drop between the source of the transistor and the rail.