Filler Cell Insertion Using Prechecked Layout Rule Matching
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Solution Overview
Problem
The existing process of filler cell insertion in integrated circuit design is inefficient and resource-intensive, often requiring iterative guess-and-check procedures that consume processing and memory resources, and is exacerbated by logic or timing changes, creating a bottleneck in the design flow.
Innovation Solution
A yield enhancer tool extracts cell characteristics, identifies vacant regions, and selects filler cells based on electrical design rules to insert them correctly, eliminating potential design rule violations, thereby optimizing the physical layout design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the place-and-route tool performs iterative guess-and-check procedures to insert filler cells, then filler cells can be inserted to eliminate electrical errors, but processing time and memory resources are significantly consumed
Solution Approach 1:
The patent applies preliminary action by performing design rule checks and identifying potential electrical errors before the actual filler cell insertion process. The system analyzes the physical layout design, detects violations in advance, and prepares a plan for filler cell placement that prevents errors rather than iteratively correcting them, thereby reducing processing time while ensuring reliability
Solution Approach 2:
The patent implements feedback by using design rule check results to guide the filler cell insertion process. The system continuously monitors the layout for electrical errors, uses this information to select appropriate filler cells, inserts them, and verifies the correction, creating a closed-loop process that efficiently eliminates errors without exhaustive iteration
2Reliability
If the place-and-route tool performs iterative guess-and-check procedures to insert filler cells, then electrical errors can be eliminated, but memory resources are significantly consumed
Solution Approach 1:
The patent applies the extraction principle by separating the design rule check function from the filler cell insertion process. The system extracts and analyzes only the necessary layout information to identify electrical errors, processes this extracted data to determine filler cell requirements, and then performs insertion based on this refined information, thereby reducing memory consumption while maintaining error elimination capability
Solution Approach 2:
The patent segments the filler cell insertion process into distinct phases: design rule analysis, error identification, filler cell selection, and insertion verification. Each segment processes only the specific data needed for that task, preventing the accumulation of unnecessary information in memory and reducing overall resource consumption while ensuring comprehensive error elimination
3Adaptability or versatility
If the filler cell insertion process is repeated after logic or timing changes, then the physical layout design can be updated, but time delay and computing resource utilization are exacerbated
Solution Approach 1:
The patent applies preliminary action by performing a targeted design rule check only on the portions of the layout affected by logic or timing changes, rather than re-analyzing the entire physical layout design. This selective approach maintains adaptability to design changes while significantly reducing the time and resources required for filler cell insertion repetition
Solution Approach 2:
The patent implements partial action by focusing the filler cell insertion process only on the specific regions of the layout that were modified by logic or timing changes. Instead of processing the entire design, the system identifies and processes only the affected areas, maintaining design update capability while minimizing time delay and computing resource utilization
Data Source
AI summary
This application discloses a computing system implementing a yield enhancer tool to extract characteristics of cells from a physical layout design for an integrated circuit, determine locations of vacant regions in the physical layout design, apply electrical design rules for manufacture of the integrated circuit to the extracted characteristics in order to identify cells in the physical layout design that would violate the electrical design rules. The computing system can select filler cells for the vacant regions based, at least in part, on extracted characteristics of the cells abutting the vacant regions and the electrical design rules, and insert the selected filler cells in the vacant regions of the physical design layout. The computing system can perform a design rule check operation, which applies the electrical design rules to the physical design layout having been inserted with the selected filler cells.