Integrated Circuit Filler Cells for Faster e-Beam Defect Inspection

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Solution Overview

Problem

Existing e-beam inspection methods in the semiconductor industry face challenges such as low inspection sensitivity, low throughput, and long analysis cycle times due to their limitations in detecting defects smaller than 30 nanometers and inefficiencies in handling non-repeating inspected patterns.

Innovation Solution

The implementation of a redesigned filler cell in the circuit layout, which includes a systematic design of experiments based on existing and potential process failure modes, enhances e-beam inspection sensitivity and throughput by converting irregular logic patterns into repeated arrays, thereby improving defect detection capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If e-beam inspection is used to detect smaller defects (down to 3nm), then measurement precision is improved, but inspection sensitivity and throughput deteriorate

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidinspection throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The inspection area is segmented into functional cells and non-functional cells. Non-functional cells are further segmented into filler cells containing repeated patterns. This segmentation allows the inspection system to focus computational resources on comparing functional cells against a library of non-functional cell patterns, enabling high-resolution defect detection while maintaining throughput through efficient pattern matching.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If e-beam inspection is used to detect smaller defects, then measurement precision is improved, but analysis cycle time increases

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidanalysis cycle time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

Non-functional cell patterns are pre-processed and stored in a library before inspection. During inspection, functional cells are compared against this pre-prepared library using efficient algorithms. This preliminary preparation of reference patterns significantly reduces the computational time required during actual inspection, thereby reducing analysis cycle time while maintaining high measurement precision.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If irregular logic patterns are inspected, then manufacturing precision is maintained, but device complexity increases due to non-repeating patterns

Engineering Contradiction:
Improvelayout accuracyVSAvoidpattern complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The invention creates copies of non-functional cell patterns (filler cells) and stores them in a library. During inspection, these copied patterns are used as reference templates to compare against functional cells. This copying approach simplifies the inspection process by replacing complex unique pattern matching with efficient template comparison, reducing device complexity while maintaining manufacturing precision.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11776948B2Integrated circuit filler and method thereof
Publication Date: 2023.10.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11776948B2 patent drawing
  • US11776948B2 patent drawing
  • US11776948B2 patent drawing

AI summary

Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.