Filler Cells for Electrical Isolation in IC Layouts
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in efficiently achieving electrical isolation between cells, leading to increased area costs and penalties due to the use of shallow trench isolation and continuous active areas with tie-down dummy gates.
Innovation Solution
The implementation of filler cells with strategically placed tie-down dummy gates to create a contiguous active area, reducing area usage and leakage currents by opportunistically adding filler cells between functional cells, thereby converting pre-defined libraries into continuous active components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double diffusion break (DDB) isolation is used to electrically isolate cells, then electrical isolation between cells is achieved, but area cost per cell increases
Solution Approach 1:
The patent introduces filler cells as intermediary elements between functional cells. These filler cells contain tie-down dummy gates that are electrically connected to power or ground, serving as mediators to block leakage currents between adjacent functional cells. This intermediary approach provides electrical isolation without requiring the extensive isolation structures of DDB, thereby reducing area cost while maintaining isolation effectiveness.
Solution Approach 2:
The patent uses dummy gates in filler cells that replicate the structure of real gates but are electrically tied down to power or ground. These copied gate structures serve the isolation function without performing logic operations, providing electrical isolation with minimal area overhead compared to full DDB isolation structures.
2Area of stationary object
If continuous active area with gate tie-down isolation is used, then area per cell is reduced, but additional tie-down elements and power connections are required
Solution Approach 1:
The patent merges the isolation function with the filler cell structure itself. The filler cells are integrated into the regular cell layout and use the same fabrication processes, combining what would otherwise be separate isolation structures with the functional cell design. This merging reduces the need for additional tie-down elements and simplifies power connections while maintaining area efficiency.
Solution Approach 2:
The filler cells serve multiple functions: they provide electrical isolation between functional cells, maintain contiguous active area for manufacturing efficiency, and can be uniformly processed through standard fabrication steps. This multi-functionality reduces the need for specialized tie-down elements and simplifies the overall device structure.
3Area of stationary object
If filler cells are strategically placed between functional cells, then area usage is reduced and leakage currents are minimized, but additional cells must be added to the layout
Solution Approach 1:
The patent segments the circuit layout into functional cells separated by filler cells. This segmentation allows the functional cells to be optimally sized for their specific functions while the filler cells provide standardized isolation interfaces. The segmented approach enables flexible layout configuration that reduces overall area usage while maintaining manageable complexity through regular placement patterns.
Data Source
AI summary
At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.