Filler Metal Polygon Allocation for IC Density and Capacitance
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Solution Overview
Problem
In deep sub-micron IC designs, the iterative process of adding filler metal polygons to meet metal density requirements often results in increased parasitic capacitance, affecting chip performance and functionality due to inadequate consideration of coupling capacitance between metal routes and filler polygons.
Innovation Solution
A method for allocating filler metal polygons during IC manufacturing, which involves computing their size using chip design layout data, identifying regions that do not meet metal density requirements, and strategically placing filler polygons to minimize coupling capacitance by optimizing their size and spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If filler metal polygons are added to meet metal density requirements, then metal density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by making filler polygons electrically connected to specific potential domains (VDD, VSS, or floating) based on their local position and characteristics. This selective connection approach allows different regions to have different electrical properties, minimizing parasitic capacitance impact while maintaining metal density requirements.
Solution Approach 2:
The patent changes the electrical state parameter of filler polygons by providing multiple connection options (VDD, VSS, floating) instead of a single fixed state. This parameter variation allows optimization of parasitic capacitance effects while maintaining the required metal density coverage.
2Quantity of substance
If filler metal polygons are placed close to metal routes to increase metal density, then metal density is improved, but coupling capacitance increases
Solution Approach 1:
The patent assigns different electrical potentials to filler polygons based on their proximity to specific metal routes. Fillers near signal routes may be connected to VDD or VSS to reduce coupling effects, while those in other regions may be floating. This localized electrical characterization reduces coupling capacitance while maintaining density.
Solution Approach 2:
The patent proactively connects filler polygons to appropriate potential domains before they can cause harmful coupling effects. By pre-establishing electrical connections (or intentional disconnections) based on predicted coupling risks, the design prevents capacitance issues rather than addressing them after occurrence.
3Quantity of substance
If iterative process is used to meet metal density requirements, then metal density is improved, but design time increases
Solution Approach 1:
The patent performs preliminary classification of filler polygons into electrical domains during the initial placement phase, rather than through iterative adjustments. By pre-determining which fillers connect to VDD, VSS, or remain floating based on layout analysis, the method achieves metal density requirements in a single pass, eliminating time-consuming iterative cycles.
Solution Approach 2:
The patent incorporates feedback mechanisms that analyze the electrical impact of filler placement and automatically adjust connections to optimize both density and capacitance. This feedback-driven approach replaces manual iterative processes with automated optimization, reducing design time while maintaining quality.
Data Source
AI summary
A technique for adding filler metal polygons in metal layers on a chip area of an IC design. In one example embodiment, this is accomplished by computing a size of a filler metal polygon using chip design layout data. One or more regions on the metal layers of the IC design that do not meet metal density requirements are then identified. The identified one or more regions are then filled with one or more filler metal polygons as a function of the metal density requirement and coupling capacitance between metal lines.