Film Substrate Cutting Pattern for Crumple-Resistant Chip Packages

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Solution Overview

Problem

Semiconductor packages using flexible film substrates face issues with crumpling or bending, which can lead to mechanical stress and electrical failures, particularly when the substrates are handled or integrated into larger modules.

Innovation Solution

Incorporating a cutting pattern on the film substrate, spaced apart from interconnection lines and dummy patterns, which are made of the same material as the connection pads and lines, helps to minimize bending by allowing controlled removal of edge regions, thus preventing crumpling and enhancing mechanical stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a flexible film substrate is used to create small and thin electronic products, then the product size and thickness are reduced, but the substrate becomes prone to crumpling and bending during handling and integration

Engineering Contradiction:
Improveproduct sizeVSAvoidsubstrate stability
Core Design Contradiction:
Volume of moving objectVSStability of the object's composition

Solution Approach 1:

The film substrate is divided into multiple regions by cutting patterns that extend from edges toward the center. These cutting patterns create segmented zones that control flexibility distribution, allowing the substrate to be handled without crumpling while maintaining overall flexibility for thin product design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the film substrate are given different mechanical properties through the cutting pattern design. Areas with cutting patterns have enhanced stability and resistance to crumpling, while areas without cutting patterns maintain flexibility. This local differentiation allows the substrate to be both handleable and structurally sound.

Inventive Principle:
Principle #3Local quality

2Volume of moving object

If the film substrate is made thinner to reduce product thickness, then the product becomes more compact, but the substrate becomes more susceptible to mechanical stress and electrical failures

Engineering Contradiction:
Improveproduct thicknessVSAvoidelectrical reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The cutting patterns segment the thin film substrate into controlled zones that prevent uncontrolled bending and crumpling. This segmentation provides mechanical support to the thin substrate, reducing stress concentration and preventing electrical failures during handling and integration into larger modules.

Inventive Principle:
Principle #1Segmentation

3Productivity

If cutting patterns are placed close to interconnection lines to maximize substrate utilization, then material usage is optimized, but the risk of electrical failures increases due to potential damage to interconnection lines

Engineering Contradiction:
Improvesubstrate utilizationVSAvoidelectrical reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The cutting patterns are strategically positioned at controlled distances from interconnection lines, creating zones of different flexibility. This local quality control ensures that cutting patterns provide mechanical support without being so close as to risk damaging interconnection lines during substrate processing or module integration.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240413071A1Semiconductor package and package module including the same
Publication Date: 2024.12.12 SAMSUNG ELECTRONICS CO LTD
  • US20240413071A1 patent drawing
  • US20240413071A1 patent drawing
  • US20240413071A1 patent drawing

AI summary

Provided is a semiconductor package including a film substrate including a sprocket hole, a semiconductor chip on the film substrate, interconnection lines connected to the semiconductor chip, a dummy pattern between the sprocket hole and the semiconductor chip, and a cutting pattern between the semiconductor chip and the dummy pattern, wherein the cutting pattern is spaced apart from the interconnection lines and the dummy pattern in a first direction.