Filter Chip Packaging With Adhesive Cavities and Via Interconnects
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Solution Overview
Problem
Conventional packaging methods for surface acoustic wave filter chips require expensive and difficult-to-process ceramic substrates, leading to large size, high cost, and low precision, which cannot meet the requirements for compact and ultra-thin packaging.
Innovation Solution
A packaging method involving a circuit substrate with pre-formed interconnecting holes and a filtering functional layer, where the filter chip is adhered to the substrate using an adhesive material to form a recessed or closed cavity, and the chip is encapsulated with conductive material for electrical connection, eliminating the need for grinding and wire bonding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ceramic substrates are used for filter chip packaging, then the structure is firm and reliable, but the substrate requires expensive grinding tools and difficult processes, resulting in low yield and high cost
Solution Approach 1:
The patent changes the material parameter of the substrate from conventional ceramic to a newly developed ceramic composite material with optimized composition and structure. This material parameter change enables the substrate to maintain firmness and reliability while being processable with simpler, less expensive tools and methods, thereby resolving the contradiction between structure firmness and manufacturing ease
Solution Approach 2:
The patent replaces expensive, difficult-to-process ceramic substrates with a more cost-effective substrate material that can be manufactured using simpler processes. The new substrate material achieves the required mechanical strength and reliability at lower cost, effectively substituting the conventional expensive ceramic substrate
2Reliability
If conventional ceramic substrates are used for filter chip packaging, then the structure is firm, but the substrate has low processing size precision, resulting in large size and thickness that cannot meet compact and ultra-thin packaging requirements
Solution Approach 1:
The patent changes the material parameters of the substrate to a new ceramic composite material that offers superior processability and dimensional precision. This material enables precise control of substrate size and thickness during manufacturing, allowing the production of compact and ultra-thin packaged filter chips while maintaining structural firmness and reliability
3Reliability
If wire bonding or flip-chip bonding processes are used for electrical interconnection, then electrical connection is achieved, but the packaging process becomes complex and time-consuming
Solution Approach 1:
The patent extracts and eliminates the complex wire bonding or flip-chip bonding processes from the packaging workflow. By designing the substrate with pre-formed conductive patterns and interconnection structures, the electrical connection is achieved directly during substrate fabrication, removing the need for separate bonding operations and significantly simplifying the overall packaging process while maintaining connection reliability
Solution Approach 2:
The patent performs the electrical interconnection preparation in advance during substrate manufacturing. Conductive traces, contact pads, and interconnection structures are pre-formed on the substrate before the filter chip is mounted. This preliminary action eliminates the need for subsequent complex bonding operations, reducing packaging process complexity and time while ensuring reliable electrical connections
4Reliability
If conventional packaging methods are used, then electrical interconnection is achieved, but the packaging size is large and thickness is increased
Solution Approach 1:
The patent merges the substrate fabrication and electrical interconnection processes into a single integrated manufacturing step. The conductive patterns and interconnection structures are formed directly on the substrate during its fabrication, eliminating the need for separate bonding processes that would increase packaging volume. This integration enables compact and ultra-thin packaging while maintaining reliable electrical connections
Solution Approach 2:
The patent transitions from three-dimensional bonding structures (wire bonds, bump connections) to planar, two-dimensional conductive patterns on the substrate surface. This dimensional change allows electrical interconnections to be made within the substrate plane rather than requiring vertical bonding structures, significantly reducing packaging thickness and overall size while maintaining connection reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces packaging difficulty, achieves smaller and thinner sizes, increases yield and productivity, and improves reliability by using a single metal material for interconnections, while allowing for simultaneous packaging and substrate selection for optimized performance.
Implementation Method 1
adhering the filter chip to the first surface of the circuit substrate via the adhesive material
Implementation Method 2
filling the interconnecting hole with a conductive material, so that the conductive material is in electrical contact with the chip pin bump or pad metal of the filter chip
Data Source
AI summary
A packaging method and package structure for a filter chip. The packaging method includes providing a circuit substrate, covering a first surface of the circuit substrate and/or filter chip with adhesive material and forming recessed cavities or closed cavities in the adhesive material. The method further includes adhering the filter chip to the first surface of circuit substrate via the adhesive material, such that surface acoustic wave transmitting regions of the filter chip correspond to the recessed cavities or closed cavities in the adhesive material to form a gap therebetween, and encapsulating the filter chip with encapsulating material. The method further includes forming interconnecting holes extending from a second surface of the circuit substrate to pins of the filter chip, filling the interconnecting holes with conductive material, so that the conductive material is in electrical contact with a chip pin bump or pad metal of the filter chip, and forming external pin pads on the second surface.