Filter Circuitry for Multi-Cycle Arbitration Stalling
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Solution Overview
Problem
In data processing apparatuses, multi-cycle arbitration becomes challenging as resources sharing a common access path may not receive access requests every clock cycle, leading to potential stalling due to inter-access timing parameters, especially when pipelined arbitration is used, where outcomes of previous arbitration operations are not known in time for decision-making.
Innovation Solution
The implementation of filter circuitry with multiple filter states, dependent on the number of pipeline stages in arbitration circuitry, ensures that each resource is associated with a unique filter state, allowing the selection of unoccupied filter states for new arbitration operations, thereby avoiding access requests that would be stalled by inter-access timing parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipelined arbitration is used to achieve continuous throughput, then productivity is improved, but reliability deteriorates due to potential stalling from inter-access timing parameters
Solution Approach 1:
The filter circuitry performs preliminary action by selecting a filter state that has not been selected for any other multi-cycle arbitration operation already in progress. This preliminary selection prevents access requests from being granted to resources that are currently being accessed by other pipeline stages, thereby preventing stalling due to inter-access timing violations while maintaining continuous throughput through pipelined arbitration
Solution Approach 2:
The filter circuitry uses feedback from the pipeline stage information to dynamically adjust which access requests are considered as candidates. By monitoring which filter states are currently selected by other pipeline stages and using this feedback to exclude those resources from candidate selection, the system ensures timing compliance is maintained while preserving high throughput
2Ease of operation
If multiple pipeline stages are used for multi-cycle arbitration, then ease of operation is improved, but device complexity increases
Solution Approach 1:
The filter circuitry acts as an intermediary between the multiple pipeline stages and the access request queue. It mediates the arbitration process by selecting appropriate filter states based on pipeline stage information, thereby simplifying the overall system operation while managing the complexity of coordinating multiple pipeline stages through a centralized filtering mechanism
Data Source
AI summary
A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states. For a new multi-cycle arbitration operation to be performed by the arbitration circuitry, the filter circuitry selects one of the filter states that has not been selected for any other multi-cycle arbitration operation already in progress within the pipeline states of the arbitration circuitry. Then, it determines as candidate access requests for the new multi-cycle arbitration operation those access requests that are seeking to access a resource associated with the selected filter state. Such an approach allows efficient multi-cycle arbitration to take place even where the resources may have inter-access timing parameters associated therewith which prevent them from being able to receive access requests every clock cycle.