Filterless Digital PLL for Jitter Rejection and Fast Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional phase-locked loops (PLLs) face a fundamental design trade-off known as the loop bandwidth trade-off, where improving jitter rejection comes at the expense of increased loop transients and vice versa, leading to inconsistent and temperamental circuit performance.
Innovation Solution
A filterless digital phase-locked loop (DPLL) is introduced, which employs a frequency detector and impulse response to control a number-controlled oscillator, measuring frequency directly and adjusting it by quantum values based on impulse magnitude, eliminating the loop bandwidth trade-off and allowing for simultaneous improvement in jitter rejection and transient response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If traditional PLL loop filter is designed to improve jitter rejection, then jitter rejection is improved, but loop transients increase
Solution Approach 1:
The patent extracts and removes the loop filter component from the traditional PLL architecture, creating a filterless DPLL. By taking out the loop filter that causes the trade-off between jitter rejection and loop transients, the invention resolves the contradiction by achieving both good jitter rejection and minimal loop transients simultaneously through direct digital frequency measurement and quantum-based frequency adjustment.
2Speed
If traditional PLL loop bandwidth is increased to improve transient response, then transient response is improved, but jitter rejection worsens
Solution Approach 1:
The invention removes the loop filter that creates the loop bandwidth trade-off, allowing the DPLL to achieve fast transient response through direct frequency measurement without sacrificing jitter rejection performance. The frequency dimension frequency detector enables rapid frequency acquisition while maintaining excellent jitter filtering through the quantum-based frequency adjustment mechanism.
3Stability of the object's composition
If traditional PLL uses loop filter to stabilize operation, then stability is improved, but device complexity increases
Solution Approach 1:
The patent eliminates the loop filter component entirely, reducing device complexity while maintaining stable PLL operation. The filterless design achieves stability through the inherent properties of the frequency dimension frequency detector and the NCO's quantum-based frequency adjustment, removing the need for additional filter components and simplifying the overall circuit architecture.
Data Source
AI summary
There is disclosed in one example a digital phase-locked loop (DPLL) circuit adapted to avoid loop-bandwidth tradeoff, the circuit including: a frequency dimension frequency detector having an external frequency input and a feedback frequency input, the frequency dimension frequency detector including circuitry to measure a frequency difference between the external frequency input and the feedback frequency input and to drive an impulse signal, wherein the impulse signal is of a first species if the difference is positive and of a second species if the difference is negative; and a number-controlled oscillator (NCO) including circuitry to drive an output clock and to adjust the frequency of the output clock responsive to the impulse signal, wherein an output of the NCO provides the feedback frequency input of the frequency dimension frequency detector.