Fin-Shaped Active Patterns in CMOS Regions
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability, performance, and integration density to meet the demands for fast speed and low power consumption, particularly in realizing improved electrical characteristics for field effect transistors.
Innovation Solution
The semiconductor device incorporates a substrate with NMOSFET and PMOSFET regions, featuring fin-shaped active patterns made of different semiconductor materials and a dummy pattern with an insulating upper layer, along with device isolation patterns that fill trenches between these structures, allowing for improved channel regions and simplified fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different semiconductor materials are used for NMOSFET and PMOSFET channel regions, then carrier mobility and electrical characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The active pattern is divided into two distinct semiconductor layers: a first semiconductor layer for the NMOSFET channel region and a second semiconductor layer for the PMOSFET channel region. This segmentation allows each transistor type to have optimized material composition (e.g., SiGe for NMOS, Si for PMOS) independently, improving carrier mobility while maintaining a structured fabrication process.
Solution Approach 2:
Different semiconductor materials with specific properties are applied to different regions: the first semiconductor layer contains materials optimized for electron mobility (NMOS channel), while the second semiconductor layer contains materials optimized for hole mobility (PMOS channel). This local optimization of material properties enhances overall device electrical characteristics without requiring complete material differentiation throughout the entire structure.
2Productivity
If dual-channel CMOS devices with different semiconductor materials are implemented, then carrier mobility is improved, but fabrication process complexity increases
Solution Approach 1:
The first and second semiconductor layers are formed in a predetermined sequence before final patterning. The first semiconductor layer is deposited and partially etched to form the NMOS active pattern, then the second semiconductor layer is deposited to form the PMOS active pattern. This preliminary layer formation simplifies the subsequent patterning step and ensures proper material distribution.
Solution Approach 2:
The fabrication process transitions from planar patterning to vertical layering by forming multiple semiconductor layers at different depths. The first semiconductor layer is formed at a lower level and the second at a higher level, allowing independent material optimization for each transistor type while using a unified patterning approach for the final active patterns.
3Reliability
If fin-shaped active patterns are used, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The active patterns are formed with fin-shaped structures that extend vertically from the substrate, creating a three-dimensional morphology. This fin geometry increases the effective channel width while maintaining a compact footprint, improving device performance. The curved or tapered fin profiles are achieved through controlled epitaxial growth and anisotropic etching processes.
Data Source
AI summary
A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern on the PMOSFET region, a dummy pattern between the NMOSFET and PMOSFET regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns. The upper portions of the first and second active patterns contain semiconductor materials, respectively, that are different from each other, and an upper portion of the dummy pattern contains an insulating material.