Semiconductor Fin Array Alignment Using PWG Displacement Measurement
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Solution Overview
Problem
Conventional methods for aligning and measuring semiconductor structures on wafers are inadequate for shrunk elements, leading to misalignment issues that are only detected after manufacturing, resulting in wasted resources and decreased throughput due to the inability to adapt measurement accuracy to the shrinking dimensions of semiconductor elements.
Innovation Solution
A method and system that form and measure fin arrays on semiconductor wafers using a patterned wafer geometry (PWG) measurement to determine the displacement between fin arrays, allowing for real-time assessment of wafer status and enabling the separation of wafers based on alignment accuracy, with a threshold value of about 1.5 nm for determining pass or fail status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional off-line measurement methods are used, then the manufacturing process is simple, but the measurement precision is insufficient for shrunk elements
Solution Approach 1:
The patent transitions from conventional 2D planar measurement to 3D depth-resolved measurement using optical coherence tomography. By introducing the depth dimension, the system can measure alignment of shrunk elements at different vertical levels within the semiconductor structure, achieving high measurement precision without proportionally increasing system complexity.
Solution Approach 2:
The patent replaces conventional mechanical contact measurement methods with non-contact optical measurement. Using light interference and coherence tomography, the system achieves nanometer-level measurement precision for shrunk elements without mechanical wear, contamination, or physical interference with the delicate semiconductor structures.
2Reliability
If alignment is not measured during manufacturing, then the manufacturing throughput is high, but misaligned wafers are only detected after manufacturing is complete
Solution Approach 1:
The patent performs alignment measurement during the manufacturing process using in-situ optical measurement capabilities. By measuring alignment of shrunk elements while they are being formed or immediately after formation, the system ensures high measurement reliability without requiring additional post-manufacturing inspection steps, thus maintaining manufacturing throughput.
Solution Approach 2:
The patent implements real-time feedback by measuring alignment during manufacturing and providing immediate results. The measurement data can be used to adjust subsequent processing parameters or identify defective wafers before they proceed to later stages, ensuring high reliability while maintaining productivity through continuous process monitoring.
3Adaptability or versatility
If conventional measurement accuracy is used, then the measurement system is simple, but it cannot adapt to the shrinking dimensions of semiconductor elements
Solution Approach 1:
The patent changes the measurement parameters by using optical coherence length and interference patterns instead of conventional mechanical or optical microscopy parameters. This allows the system to achieve nanometer-level precision required for shrunk elements while maintaining a relatively simple optical measurement setup that can adapt to different element dimensions.
Solution Approach 2:
The patent introduces depth resolution as an additional measurement dimension, allowing the system to measure alignment of shrunk elements at different vertical positions within the semiconductor structure. This dimensional enhancement provides adaptability to three-dimensional shrunk elements without sacrificing measurement accuracy.
4Productivity
If misaligned wafers continue through manufacturing, then no additional measurement steps are needed, but manufacturing resources and time are wasted
Solution Approach 1:
The patent performs alignment measurement at an early stage during manufacturing, allowing defective wafers to be identified before significant processing resources are consumed. By measuring alignment of shrunk elements while the wafer is still in the manufacturing process, the system can stop processing of defective wafers early, reducing material waste and improving overall productivity.
Solution Approach 2:
The patent implements real-time feedback control by monitoring alignment during manufacturing and providing immediate information about wafer quality. This allows the manufacturing system to adjust processing parameters or divert defective wafers before they complete the full manufacturing cycle, reducing waste of time and resources while maintaining high throughput for good wafers.
Data Source
AI summary
The present disclosure relates to a manufacturing and measuring system for semiconductor structures on a wafer. The system includes a process chamber and a measuring device. The process chamber is configured to perform operations of forming a first fin array in a bank of a die of a wafer and forming a second fin array on the first fin array. The measuring device is configured to perform a pattern wafer geometer (PWG) measuring on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array, and further configured to determine a status of wafer according to the displacement.