Semiconductor Fin Array Alignment Using PWG Wafer Measurement
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Solution Overview
Problem
Conventional semiconductor manufacturing methods struggle with alignment issues due to shrinking element dimensions, leading to misaligned wafers that are only detected after manufacturing, resulting in wasted resources and decreased throughput.
Innovation Solution
A method and system for manufacturing and measuring semiconductor structures that involve forming fin arrays in multiple layers on a wafer, performing patterned wafer geometry (PWG) measurements to determine displacement between these arrays, and using a lookup table to assess wafer status based on displacement thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional off-line alignment examination is used, then manufacturing process is simple, but alignment accuracy is insufficient for shrunk elements and defects are only detected after manufacturing
Solution Approach 1:
The patent performs PWG measurement on the wafer immediately after fin array formation but before completing the entire manufacturing process. This preliminary measurement allows alignment defects to be detected early, enabling timely corrective actions before resources are wasted on defective wafers.
Solution Approach 2:
The patent replaces conventional mechanical/off-line alignment examination with an optical PWG measurement system that can perform high-precision measurements in-situ during the manufacturing process, achieving both high measurement precision and real-time detection capability.
2Productivity
If conventional off-line measurement is used, then measurement system is simple, but manufacturing resources and time are wasted on misaligned wafers
Solution Approach 1:
The patent implements a feedback mechanism where PWG measurement results are obtained and used to determine wafer status in real-time. This feedback loop enables immediate identification of misaligned wafers, allowing the manufacturing system to adjust processes or discard defective wafers before further resource investment, thereby improving productivity and reducing waste.
3Measurement precision
If real-time PWG measurement is performed, then alignment detection accuracy is improved, but measurement complexity increases
Solution Approach 1:
The patent extracts only the critical alignment parameters (displacement between fin arrays) for measurement using PWG technique, rather than performing comprehensive measurements of all wafer parameters. This selective measurement approach maintains high precision for critical dimensions while avoiding the complexity of measuring all possible parameters.
Data Source
AI summary
The present disclosure provides a manufacturing method for semiconductor structures. The method includes the following operations: receiving a wafer having a plurality of dies; respectively forming a plurality of semiconductor structures in a plurality of banks in each of the plurality of dies, wherein each of the semiconductor structure includes a first fin array and a second fin array disposed above the first fin array; performing a PWG measurement on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array; and according to the displacement, determining a status of wafer.