Fin Structure Aspect Ratio Trapping via Encapsulating Dielectric
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Solution Overview
Problem
The miniaturization of integrated circuits requires transistors with higher drive currents, which existing non-planar semiconductor devices like FinFETs struggle to achieve due to limitations in fin structure geometry and material defects in III-V semiconductor materials.
Innovation Solution
A method of forming fin structures using replacement gate structures and epitaxial growth of III-V semiconductor materials, where an encapsulating dielectric is used to expose a growth surface for selective etching, allowing for the growth of functional fin structures with reduced defect density through aspect ratio trapping (ART) techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If FinFET structures are used to increase drive current, then transistor performance is improved, but manufacturing precision and defect density in III-V semiconductor materials worsen
Solution Approach 1:
The fin structure fabrication is divided into multiple stages: forming replacement fins, depositing encapsulating dielectric, creating openings, and selective etching. This segmentation allows each step to be optimized independently, reducing cumulative defects while maintaining the high drive current capability of FinFET structures.
Solution Approach 2:
The encapsulating dielectric is deposited over the replacement fin structures before the final fin formation. This preliminary action protects the underlying structures and defines the final fin geometry through the opening pattern, enabling better control over fin dimensions and reducing manufacturing variability.
2Productivity
If miniaturization is pursued to increase integration density, then circuit capacity is improved, but drive current capability deteriorates
Solution Approach 1:
The method enables precise control of fin dimensions (width, height, spacing) through the encapsulating dielectric thickness and opening pattern geometry. This parameter control allows optimization of drive current at each size node, maintaining performance despite miniaturization. The selective etching process also enables aspect ratio control to optimize current flow.
Solution Approach 2:
The invention transitions from planar transistors to three-dimensional FinFET structures, utilizing the vertical dimension to increase effective channel width without increasing footprint. This dimensional transition maintains drive current capability while achieving higher integration density through vertical scaling.
3Reliability
If replacement gate structures are used to enable III-V material growth, then electron mobility is improved, but process complexity increases
Solution Approach 1:
The encapsulating dielectric serves as an intermediary that enables the replacement gate process. It allows the gate structure to be formed after the fin structures are in place, facilitating epitaxial growth of III-V materials on the fin surfaces. This intermediary layer simplifies the integration of complex materials processes with standard CMOS fabrication.
Solution Approach 2:
The replacement gate structure is formed preliminarily to define the gate region before the final III-V fin structures are grown. This preliminary gate formation enables subsequent selective epitaxial growth on the fin surfaces, ensuring proper alignment and reducing process complexity compared to attempting direct fin formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of fin structures with high electron mobility and low defect density, enhancing drive currents in transistors and supporting continued CMOS scaling.
Implementation Method 1
An encapsulating dielectric is formed on the substrate and the at least one replacement gate structure, wherein the encapsulating dielectric encapsulates the replacement fin structure
Implementation Method 2
The replacement fin structure is then etched selectively to the encapsulating dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric
Implementation Method 3
Functional fin structures of a second semiconductor material are epitaxially grown on the growth surface of the substrate substantially filling the fin opening
Data Source
AI summary
A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.