Fin-Based Dual-Bit NVM Structures for Storage Density
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Solution Overview
Problem
Conventional flash memory cells face challenges in increasing storage density and manufacturing complexity due to the need for precise voltage settings and complicated circuitry for dual-bit storage, which is not adequately addressed by scaling down geometry alone.
Innovation Solution
The development of fin-based dual-bit nonvolatile memory (NVM) structures with a primary fin structure, adjacent fin structures, and self-aligned floating gates, along with a control gate, allows for improved storage density and simplified manufacturing by using three parallel fins to form dual-bit NVM structures, enabling precise program/erase operations through separate program and erase probes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional flash memory cells are scaled down to increase storage density, then storage capacity increases, but manufacturing precision requirements become excessively stringent
Solution Approach 1:
The patent transitions from planar 2D memory cells to three-dimensional fin-based structures. The fin structures extend vertically from the substrate, creating additional spatial dimension for storage. Multiple floating gates are positioned at different heights and locations around the fin, enabling dual-bit storage without requiring proportionally smaller feature sizes, thus avoiding the need for excessively precise lithography.
Solution Approach 2:
The memory cell is segmented into distinct functional regions: primary fin structure for charge storage, adjacent fin structures for program/erase gates, and control gates. This segmentation allows each component to be optimized independently and simplifies the manufacturing process by enabling separate formation of different functional elements through selective doping and gate deposition.
2Quantity of substance
If dual-bit flash memory cells are implemented with precise voltage settings, then storage capacity doubles, but circuitry complexity increases significantly
Solution Approach 1:
The control gate serves multiple functions: it controls the primary fin structure for read operations and also controls the adjacent fin structures during program and erase operations. The adjacent fin structures function as both program gates and erase gates depending on the operation mode. This multi-functionality reduces the need for separate dedicated circuitry for each function, thereby simplifying overall device complexity while maintaining dual-bit storage capability.
3Quantity of substance
If conventional flash memory cells are used, then manufacturing process is simple, but storage density is limited
Solution Approach 1:
The fin structures are formed using self-aligned processes where the adjacent fin structures automatically position themselves relative to the primary fin structure. The selective doping process inherently creates the correct junction regions without requiring additional alignment steps. This self-alignment and self-organization reduce manufacturing complexity despite the three-dimensional structure, maintaining ease of manufacture while achieving higher storage density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances storage density and manufacturing efficiency by allowing for high-speed, non-volatile dual-bit storage without the need for precise lithography, improving program/erase endurance and simplifying the circuitry complexity, thus overcoming the limitations of conventional flash memory cells.
Implementation Method 1
These voltages excite the electrons such that they push through the thin oxide layer and are trapped on the floating gate. Consequently, the gate carries a negative charge.
Implementation Method 2
A conventional flash memory cell is programmed by applying a high voltage to the control gate or the word line and a high voltage to the drain by way of the bit line. These voltages excite the electrons such that they push through the thin oxide layer
Implementation Method 3
A flash memory cell programmed with a 'zero' may be erased by applying a high voltage to the gate and leaving the drain or bit line open or floating. Thus, the excess electrons that were trapped on the floating gate now move to the gate so that the floating gate is again neutral
Data Source
AI summary
Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.