Fin-Shaped Active Region Buffer Layer for Lattice-Mismatch Control
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration density and operation speed due to limitations in strain application and lattice mismatch between fin-shaped active regions and source/drain regions, leading to issues like cracks and crystal defects.
Innovation Solution
A semiconductor device design featuring a fin-shaped active region with a gate insulating film, gate electrode, insulating spacers, source/drain regions made of compound semiconductor materials, and a buffer layer to reduce lattice mismatch and apply compressive stress, thereby enhancing carrier mobility and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If source/drain regions with different group semiconductor materials are used to apply strain, then operation speed increases, but lattice mismatch causes cracks and crystal defects
Solution Approach 1:
A buffer layer comprising a first buffer region and a second buffer region is introduced as an intermediary between the fin-shaped active region and the source/drain regions. The first buffer region has a lattice constant intermediate between the fin-shaped active region and the source/drain regions, while the second buffer region has a lattice constant intermediate between the first buffer region and the source/drain regions. This gradient structure gradually transitions the lattice constant, reducing mismatch and preventing cracks while maintaining the strain-induced high operation speed.
2Reliability
If compound semiconductor materials are used in source/drain regions, then carrier mobility improves, but manufacturing complexity increases
Solution Approach 1:
The patent systematically varies the lattice constant parameter across multiple buffer regions to bridge the mismatch between group IV fin-shaped active regions and group III-V or group II-VI compound semiconductor source/drain regions. By creating a gradient structure where the first buffer region has an intermediate lattice constant and the second buffer region has another intermediate lattice constant, the patent enables the use of high-mobility compound semiconductors while managing manufacturing complexity through a structured, multi-layer approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design increases the operation speed of transistors by applying compressive stress and reducing lattice mismatch, limiting cracks and improving the crystallinity of source/drain regions, thus enhancing the overall reliability and performance of the semiconductor device.
Implementation Method 1
a buffer layer located between the fin-shaped active region and the one pair of first source/drain regions, the buffer layer an upper buffer layer on a lower buffer layer, the lower buffer layer including a group III-V compound semiconductor material or a group II-VI compound semiconductor material that is amorphous, and the upper buffer layer including a compound semiconductor material including first atoms and second atoms from different groups
Implementation Method 2
a buffer layer located between the fin-shaped active region and the one pair of first source/drain regions... applying compressive stress and reducing lattice mismatch
Data Source
AI summary
A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.