Fin Structure Buried Power Rail Layout Without Via Landing
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Solution Overview
Problem
The miniaturization of CMOS FinFET devices faces challenges due to the conductive via landing issue, which affects the reliability of electrical connections and increases the size of the semiconductor device, making it difficult to further reduce the device size while maintaining reliable performance.
Innovation Solution
The implementation of a buried power rail structure, where conductive rails are formed in a same layer as polysilicon and metal lines, allowing electrical connection without conductive vias, thereby reducing the device size and enhancing reliability by eliminating the conductive via landing issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive vias are used for electrical connections in miniaturized devices, then electrical connection reliability deteriorates due to the conductive via landing issue, but device size cannot be reduced further
Solution Approach 1:
The patent extracts and eliminates the conductive via structure from the interconnect system. By removing the via layer entirely and replacing it with planar metal lines formed in the same layer as polysilicon, the solution directly addresses the conductive via landing issue while enabling further device miniaturization without compromising electrical connection reliability
Solution Approach 2:
The patent transitions from a vertical interconnect architecture (using vias to connect different layers) to a planar interconnect architecture (using metal lines in the same layer as polysilicon). This dimensional change eliminates the need for vertical via connections and their associated landing issues, allowing for more reliable electrical connections in miniaturized devices
2Length of moving object
If device size is reduced for miniaturization, then manufacturing complexity increases due to the conductive via landing issue, but further size reduction becomes difficult
Solution Approach 1:
The patent removes the complex via formation and alignment processes from the manufacturing workflow. By eliminating the via layer and using simple planar metal line deposition in the same layer as polysilicon, the solution significantly reduces manufacturing complexity while enabling continued device size reduction
Solution Approach 2:
The patent changes the structural parameters of the interconnect system by transitioning from three-dimensional via structures to two-dimensional planar metal lines. This parameter change simplifies the manufacturing process by eliminating multi-layer alignment requirements and via formation steps, thereby reducing manufacturing complexity
Data Source
AI summary
A method for forming a semiconductor device includes: forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; and forming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure.