Fin Capacitor Structure for High-Density FinFET Decoupling
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Solution Overview
Problem
As semiconductor IC dimensions shrink, the capacitance density of traditional metal-oxide-metal (MOM) capacitors decreases significantly, leading to a need for improved decoupling capacitor designs that are compatible with transistor manufacturing processes and can maintain or increase capacitance density.
Innovation Solution
The development of fin capacitors, which utilize silicon fins and dielectric materials within the FinFET manufacturing process to create a structure with increased capacitance density by reducing the pitch between electrical conductors and using insulating materials like silicon oxide, resulting in higher overlap and fringe capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC dimensions are shrunk, then device integration is improved, but capacitance density of MOM capacitors decreases significantly
Solution Approach 1:
The patent transitions from planar MOM capacitor structures to three-dimensional FinFET-based capacitor structures. By utilizing the vertical fin structure with multiple gates surrounding the channel, the capacitor achieves increased capacitance density through additional dimensional space, effectively decoupling the scaling of device integration from capacitance density maintenance.
2Length of moving object
If metal layers or polysilicon layers are made thinner, then IC dimensions are reduced, but capacitance density decreases about 30% per technology node
Solution Approach 1:
The invention utilizes the vertical dimension of the FinFET structure, where the fin extends upward from the substrate with gates wrapping around it. This three-dimensional configuration allows capacitance to be generated through lateral overlap areas rather than relying solely on thin vertical layer thickness, thereby maintaining capacitance density even as layer dimensions are reduced.
Solution Approach 2:
The patent changes the geometric parameters of the capacitor structure by using the fin height, fin width, and gate overlap dimensions instead of traditional planar layer thickness parameters. By optimizing these new parameters, the capacitor maintains high capacitance density despite reductions in traditional layer thicknesses associated with technology scaling.
3Ease of manufacture
If traditional MOM capacitor designs are used, then manufacturing process compatibility is maintained, but capacitance density decreases with scaling
Solution Approach 1:
The FinFET structure serves dual purposes: it functions as both the transistor active device and as the capacitor structure. The same fin and gate structures used for transistor operation are utilized to create the capacitor, eliminating the need for separate capacitor fabrication processes and maintaining full compatibility with existing FinFET manufacturing workflows while achieving superior capacitance density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The fin capacitor design achieves a capacitance density increase of up to 238% compared to MOM capacitors, addressing the decreasing capacitance issue in smaller IC dimensions while being compatible with existing FinFET manufacturing processes.
Implementation Method 1
The capacitances of these capacitors depend on the dimensions of the conducting portions
Implementation Method 2
using insulating materials like silicon oxide
Data Source
AI summary
A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.