Fin Capacitors With Local Quality Dielectric Contact
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high capacitance and integration density to meet the demands for fast speed and low power consumption while maintaining reliability and multiple functions.
Innovation Solution
The semiconductor device incorporates fin capacitors with specific structural features, including active fins, dielectric layers, and gate electrodes, where the second dielectric layer directly contacts the bottom surface of the second trench and covers top and side surfaces of the second active fins, enhancing capacitance by increasing the active area for charge storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the second dielectric layer is in direct contact with the bottom surface of the second trench and covers top and side surfaces of the second active fins, then capacitance is enhanced by increasing the active area for charge storage, but device complexity increases due to different structural configurations between first and second regions
Solution Approach 1:
The patent applies local quality by creating different structural configurations in different regions of the substrate. The first region contains transistors with device isolation layers filling trenches between active fins, while the second region contains capacitors where the dielectric layer is in direct contact with the bottom surface of trenches and covers top and side surfaces of active fins. This regional differentiation allows optimization of each region for its specific function (transistor operation vs. capacitance storage) without compromising overall device performance.
Solution Approach 2:
The patent utilizes dimensionality change by extending the dielectric layer in the second region to cover not only the top surfaces but also the side surfaces of the active fins. This three-dimensional configuration increases the effective surface area available for charge storage, thereby enhancing capacitance. The dielectric layer wraps around the active fins, utilizing vertical and lateral dimensions simultaneously to maximize storage capacity within the available space.
2Productivity
If fin capacitors with higher capacitance are implemented, then integration density and performance are improved, but manufacturing precision requirements increase due to selective trench formation and dielectric layer deposition
Solution Approach 1:
The patent applies preliminary action by forming both first and second trenches simultaneously across the substrate before subsequent selective processing. The trenches are created in advance with predetermined depths and positions, establishing the structural framework for both transistor and capacitor regions. This preliminary trench formation allows subsequent steps to focus on selective dielectric layer deposition and material filling, reducing the overall number of high-precision alignment steps required.
Solution Approach 2:
The patent implements local quality through selective dielectric layer deposition in different regions. In the first region, device isolation layers are deposited to fill trenches between active fins for transistor isolation. In the second region, the dielectric layer is deposited to directly contact the bottom surface of trenches and cover the top and side surfaces of active fins for capacitance enhancement. This selective regional processing allows optimization of manufacturing precision requirements for each specific function.
Data Source
AI summary
A semiconductor device with fin capacitors is disclosed. The device includes a substrate including a first region and a second region; first and second active fins at the first and second regions, respectively, of the substrate; a device isolation layer in a first trench between the first active fins; first and second gate electrodes that cross the first and second active fins, respectively; a first dielectric layer between the first active fins and the first gate electrode to extend along the first gate electrode, and a second dielectric layer between the second active fins and the second gate electrode to extend along the second gate electrode. The first dielectric layer is spaced apart from a bottom surface of the first trench by the device isolation layer between the bottom surface of the first trench and the first dielectric layer. The second dielectric layer is in direct contact with a bottom surface of a second trench between the second active fins.