Fin Critical Dimension Control via Dummy Fin Retention
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Solution Overview
Problem
The challenge in fabricating FinFETs is the variation in fin critical dimensions (CDs) due to different dielectric loading effects in various device regions, leading to inconsistent device performance, especially with the high temperature annealing of flowable dielectric materials which causes silicon atom consumption and fin shrinkage.
Innovation Solution
Forming STI structures before removing nonfunctional dummy fins ensures all semiconductor fins experience a uniform dielectric loading environment during annealing, thereby minimizing fin CD variations and enhancing consistency across different device regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature annealing is performed on flowable dielectric materials, then device performance is improved, but fin critical dimensions shrink and vary across different device regions
Solution Approach 1:
The patent applies preliminary action by forming STI structures before removing dummy fins, ensuring that all fins experience uniform dielectric loading during the subsequent high temperature annealing process. This sequence of operations prevents fin CD variation while maintaining the benefits of annealing for device performance
Solution Approach 2:
The patent uses local quality by maintaining different dielectric loading conditions in different device regions through the presence of dummy fins in non-active regions. This creates a uniform annealing environment across all fins while allowing different regions to have different functional requirements
2Device complexity
If dummy fins are removed early in the process, then manufacturing complexity is reduced, but fin critical dimension uniformity deteriorates due to non-uniform dielectric loading
Solution Approach 1:
The patent delays the removal of dummy fins until after the STI formation and annealing processes are complete. This preliminary retention of dummy fins ensures uniform dielectric loading during critical process steps, and only removes them when they are no longer needed for process uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more uniform fin CDs and consistent device performance by standardizing the dielectric loading environment, reducing the impact of high temperature annealing on fin dimensions across different regions.
Implementation Method 1
high temperature annealing of flowable dielectric materials which causes silicon atom consumption and fin shrinkage
Data Source
AI summary
A semiconductor structure includes an active semiconductor fin having a first height, a dummy semiconductor fin adjacent to the active semiconductor fin and having a second height less than the first height, an isolation structure between the active semiconductor fin and the dummy semiconductor fin, and a dielectric cap over the dummy semiconductor fin. The dielectric cap is separated from the active semiconductor fin.