Fin-Shaped Transistor Channel Formation With Etch-Stop STI Recess
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Solution Overview
Problem
Current methods for forming nanoscale transistor structures, such as gate-all-around (GAA) or nanowire (NW) transistor structures, result in irregular channel shapes due to local oxidation of fin structures, leading to instability and lack of control over device properties.
Innovation Solution
The method involves a layer stack with a patterned hard mask and etch stop layers, where the etch stop layers and virtual buffer layers are used to selectively recess the shallow trench isolation structures, allowing for better control over the channel shape and stability of the transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If local oxidation of the lower surface of a fin structure is used to form GAA or NW transistor structures, then nanoscale structures can be produced, but the channel shape becomes irregular and unstable
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial layer and etch stop layers before the final channel structure is created. The etch stop layers are positioned at specific depths to predefine the channel shape, ensuring that when material is removed, the channel maintains a regular, controlled geometry rather than becoming irregular through oxidation. This preliminary structuring prevents the stability issues that arise from uncontrolled oxidation processes.
2Manufacturing precision
If etch stop layers and virtual buffer layers are used to selectively recess STI structures, then channel shape control is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the layer stack into multiple functional layers including etch stop layers, virtual buffer layers, and sacrificial layers. Each layer serves a specific purpose in controlling the recess process and defining the channel geometry. This segmentation allows for precise control of the channel shape while making the complex fabrication process more manageable through systematic layer-by-layer construction.
Solution Approach 2:
The patent uses intermediary layers (etch stop layers and virtual buffer layers) that mediate between the STI structures and the final channel formation. These intermediary layers enable selective recessing of STI structures without directly affecting the channel region, providing a controlled mechanism to achieve precise channel shapes while isolating the complexity of the multi-layer structure from the final device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reproducibility and stability of the transistor devices by defining a controlled fin-shaped channel structure, improving the predictability and consistency of device characteristics.
Implementation Method 1
selectively removing the central portion of the layer stack, characterized by removing the virtual buffer layer
Data Source
Figure 1~1(f)
Figure 1(g)~1(i)
Figure 2~2(f)
AI summary
A method for forming a transistor structure comprising a fin-shaped channel structure, comprising: - providing a layer stack embedded laterally in STI structures; - recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion; - providing one or more protection layers on the upper portion of the layer stack; - after providing one or more protection layers, further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack; - removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other; wherein providing the layer stack comprises providing an etch stop layer at a position directly below the channel portion, such that the freestanding upper part of the layer stack comprises an etch stop layer at its lower surface after selectively removing the central portion.