Fin Channel Ge Diffusion for Multiple Threshold Voltages
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling planar devices like MOSFETs, which are addressed by developing non-planar transistors such as GAA and FinFETs, but further improvements are needed to meet increasing functional density and high-mobility channel requirements.
Innovation Solution
A semiconductor device structure is formed by depositing a semiconductor liner layer with different materials on fin structures, followed by capping layers of varying compositions, and a thermal process to drive germanium into these structures, creating distinct diffusion profiles that enable multiple threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar devices like MOSFETs are scaled down, then functional density increases, but manufacturing precision deteriorates due to scaling challenges
Solution Approach 1:
The patent transitions from planar (flat) device structures to non-planar structures including FinFETs with vertical fins and GAA transistors with three-dimensional channel structures. This curvature and verticality enable continued scaling by exploiting the third dimension, improving gate control and reducing short-channel effects while maintaining manufacturability at smaller nodes
Solution Approach 2:
The invention moves device architecture from two-dimensional planar structures to three-dimensional non-planar structures. FinFETs introduce vertical fins extending from the substrate, and GAA transistors utilize vertically stacked channels, effectively adding dimensional complexity to overcome planar scaling limitations and achieve higher functional density
2Reliability
If non-planar transistors like FinFETs and GAA are used, then current leakage reduces and current flow increases, but device complexity increases
Solution Approach 1:
The patent divides the channel region into multiple segments - FinFETs use vertically segmented fins with gate electrodes wrapping around them, while GAA transistors use multiple stacked channel segments. This segmentation improves gate control over the channel, reducing short-channel effects and current leakage while maintaining manageable device complexity through modular construction
Solution Approach 2:
The invention employs composite material structures including silicon-germanium (SiGe) alloys for channel regions, high-k dielectric materials for gate insulators, and metal gates. These composite materials enable the non-planar structures to achieve superior electrical characteristics and current control while managing the inherent complexity through material property optimization
3Speed
If high-mobility channels are used, then carrier mobility increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes in material composition, particularly varying germanium content in silicon-germanium channel layers, to optimize carrier mobility. By adjusting the germanium concentration gradient and crystalline orientation parameters during deposition, high carrier mobility is achieved while managing manufacturing precision requirements through controlled parameter variation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of semiconductor devices with a plurality of threshold voltages, enhancing carrier mobility and reducing channel resistance, and can be integrated into existing CMOS fabrication flows.
Implementation Method 1
performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure, wherein a concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region
Data Source
AI summary
An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.