Fin Channel Isolation Using Passivation-Blocked Epitaxy
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Solution Overview
Problem
In semiconductor device fabrication, early channel cut processing leads to issues such as iso-dense loading and defects during manufacturing, particularly in shallow trench isolation and dummy gate formation, affecting device yield and performance.
Innovation Solution
The method involves patterning a passivation layer to selectively prevent source/drain epitaxy at selected channels after dummy gate patterning, thereby isolating the channels and avoiding early channel cut processing, which allows for improved channel-to-channel spacing and reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If early channel cut processing is performed, then channel isolation is achieved, but iso-dense loading and defects occur during shallow trench isolation and dummy gate formation
Solution Approach 1:
The passivation layer is formed over the fins before source/drain epitaxy to prevent epitaxial growth in specific regions. This preliminary protective action allows channels to remain connected during fabrication, avoiding the iso-dense loading problems that occur with early channel cut processing, while still enabling subsequent channel isolation when needed.
Solution Approach 2:
The passivation layer acts as an intermediary material that selectively prevents source/drain epitaxy at selected channels. By using this intermediate layer, the patent avoids direct channel cutting and its associated defects, while achieving the necessary channel isolation through selective removal of the passivation layer in specific regions.
2Productivity
If channel-to-channel spacing is reduced for higher density, then fabrication complexity increases, but manufacturing precision deteriorates
Solution Approach 1:
The passivation layer is selectively removed at specific channels using targeted etching processes, allowing different regions of the device to have different properties. Channels that require isolation have the passivation removed, while channels meant to remain connected retain the passivation layer, enabling precise local control over channel behavior despite reduced spacing.
Solution Approach 2:
The patent changes the physical and chemical parameters of the passivation layer through selective etching processes. By controlling etching conditions such as chemistry, temperature, and duration, the patent achieves precise removal of passivation at selected channels while maintaining it elsewhere, enabling high-density fabrication with maintained precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device yield by preventing iso-dense loading and reducing defects, leading to improved manufacturing efficiency and performance in semiconductor devices like FinFETs and GAAFETs.
Implementation Method 1
Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation
Data Source
AI summary
A method of fabricating a semiconductor device is described. The method includes forming a plurality of fins over a substrate, and forming dummy gates patterned over the fins. Each dummy gate has a spacer on sidewalls of the patterned dummy gates. The method also includes forming recesses in the fins by using the patterned dummy gates as a mask, forming a passivation layer over the fins and in the recesses in the fins, and patterning the passivation layer to leave a remaining passivation layer in some of the recesses in the fins.