Semiconductor Fin Contact Layout for Lower Source/Drain Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in improving processing and manufacturing efficiency as the complexity of semiconductor integrated circuits (ICs) increases with scaling down, requiring innovative methods to manage complex manufacturing processes effectively.
Innovation Solution
The method involves forming semiconductor device structures by sequential processes including the formation of semiconductor layers, patterning fins, and forming dielectric features, followed by the deposition of sacrificial gate stacks and spacer formation, with subsequent etching and epitaxial layer formation to create source/drain regions, and finally replacing sacrificial gate stacks with gate stacks, enhancing the semiconductor device structure's architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent introduces mandrel structures that segment the processing area into distinct regions (first semiconductor fins, second semiconductor fins, dielectric features) that can be formed and processed independently. This segmentation allows complex multi-material structures to be built through sequential, modular deposition and etching steps, making the overall complex process more controllable and manufacturable at scaled dimensions
Solution Approach 2:
The mandrel structures serve as preliminary placeholders that are formed first, before the actual semiconductor fins and dielectric features are created. These pre-formed mandrels guide subsequent processing steps, enabling precise positioning of multiple fin types and dielectric regions without requiring complex real-time alignment, thus reducing processing complexity despite scaled geometry
2Productivity
If functional density is increased, then more devices per chip area are achieved, but manufacturing precision requirements increase
Solution Approach 1:
The mandrel structures act as intermediary elements that mediate between the deposition process and the final fin/dielectric feature formation. By depositing materials conformally on these mandrels and then performing selective removal, the patent achieves precise dimensional control of multiple fin types and dielectric features with different materials and geometries, meeting stringent manufacturing precision requirements for high functional density
Solution Approach 2:
The patent employs nested structures where dielectric features are formed between and around semiconductor fins, with multiple layers of materials deposited in nested sequences. This nesting approach allows compact arrangement of multiple device components within limited chip area, increasing functional density while maintaining precise dimensional control through conformal deposition on each nested layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the semiconductor device structure's efficiency and reduces electrical resistance by optimizing the dimensions and contact areas of source/drain epitaxial features and conductive contacts, thereby enhancing the overall performance and manufacturing efficiency.
Implementation Method 1
forming a first source/drain epitaxial feature over the recessed first semiconductor fin and a second source/drain epitaxial feature over the recessed second semiconductor fin
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The method includes forming first and second semiconductor fins in an NMOS region and a PMOS region, respectively, forming a dielectric feature between the first and second semiconductor fins, recessing the first and second semiconductor fins, forming first and second source/drain epitaxial features over the recessed first and second semiconductor fins, respectively, depositing an interlayer dielectric layer over the first and second source/drain epitaxial features, and forming a first opening in the interlayer dielectric layer to expose a first portion of the first source/drain epitaxial feature and a second opening in the interlayer dielectric layer to expose a first portion of the second source/drain epitaxial feature. The first and second openings are separated by a distance that is about 1.5 times to about 2 times a width of the dielectric feature.