Fin Cut Dummy Gate Collapse Prevention in FinFET Fabrication
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Solution Overview
Problem
During fin field-effect transistor (finFET) fabrication, channel strain is caused by fin cutting, leading to mobility degradation, and the replacement gate process faces issues with dummy gate collapse due to high-aspect-ratio structures on shallow trench isolation (STI), resulting in undesirable effects like spacer merging and incomplete etch.
Innovation Solution
A method is introduced where a dummy gate material is deposited to pin the lattice constant of fins, followed by a fin cut technique that reduces the aspect ratio of dummy gates on STI, minimizing bending and collapse, and maintaining strain by locking it in before cutting. This involves patterning fins, forming an oxide layer, depositing dummy gate material, creating trenches, and filling them with dielectric to reduce the aspect ratio of dummy gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If fins are cut after patterning to create individual devices, then device separation is achieved, but strain relaxation occurs causing mobility degradation
Solution Approach 1:
The patent applies preliminary action by forming the dummy gate material over the fins before performing the fin cut. This preliminary deposition of dummy gate material locks in the strain in the fin before cutting, preventing strain relaxation that would otherwise occur when fins are separated. The dummy gate material serves as a protective layer that maintains the strained state of the fin during the subsequent cutting process.
2Ease of manufacture
If dummy gates are formed on STI oxide between cut fin ends, then replacement gate process is enabled, but high-aspect-ratio dummy gates collapse due to undercutting
Solution Approach 1:
The patent applies parameter changes by modifying the aspect ratio of dummy gates formed on STI oxide. This is achieved by filling the trench with dielectric material to a level above the fin, which reduces the height of the dummy gate relative to its width. By changing the geometric parameters (reducing aspect ratio), the dummy gate becomes structurally stable and resistant to collapse during the replacement gate process.
Solution Approach 2:
The patent applies preliminary anti-action by proactively preventing dummy gate collapse before it can occur. The method involves forming the dummy gate material, then filling the trench with dielectric material to reduce the aspect ratio and add structural support. This preliminary reinforcement prevents the undercutting and collapse that would otherwise occur during subsequent processing steps.
3Device complexity
If dummy gates have high aspect ratio on STI, then replacement gate structure is formed, but spacer merging and incomplete etch occur
Solution Approach 1:
The patent applies parameter changes by reducing the aspect ratio of dummy gates through dielectric filling. By changing the geometric parameters (reducing height relative to width), the dummy gate structure becomes more robust, preventing spacer merging and enabling complete spacer etch during the replacement gate process. This parameter modification directly addresses the manufacturing precision issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces strain relaxation and prevents dummy gate collapse, maintaining device performance by anchoring gates with fins and reducing aspect ratios, thereby enhancing the finFET fabrication process.
Implementation Method 1
depositing a first dummy gate material onto the oxide layer over the at least one fin, wherein the first dummy gate material serves to pin a lattice constant of the at least one fin
Implementation Method 2
partially filling the trench with a first dielectric to a level above the at least one fin; depositing a second dummy gate material into the trench on top of the first dielectric; patterning the first dummy gate material and the second dummy gate material into dummy gates, wherein at least one of the dummy gates is disposed on the first dielectric and at least another one of the dummy gates is disposed on the at least one fin, and wherein the at least one dummy gate disposed on the first dielectric has an aspect ratio less than an aspect ratio of the at least one dummy gate disposed on the at least one fin
Data Source
AI summary
The present invention provides fin cut techniques in a replacement gate process for finFET fabrication. In one aspect, a method of forming a finFET employs a dummy gate material to pin a lattice constant of patterned fins prior to a fin cut thereby preventing strain relaxation. A dielectric fill in a region of the fin cut (below the dummy gates) reduces an aspect ratio of dummy gates formed from the dummy gate material in the fin cut region, thereby preventing collapse of the dummy gates. FinFETs formed using the present process are also provided.