Fin Cutting During Replacement Gate Etch in FinFETs

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Solution Overview

Problem

Current FinFET manufacturing processes face challenges in efficiently cutting fins during replacement gate formation, leading to issues like dense/iso loading and strain relaxation, which affect the uniformity and electrical properties of the fins.

Innovation Solution

The process involves forming vertical fins over a semiconductor layer, depositing an oxide, applying a cutting mask, removing the oxide from exposed portions, and etching a replacement gate stack to cut the fins, thereby simplifying the fin cut process and inhibiting strain relaxation by pinning the fins with the replacement dummy gate oxide and amorphous silicon.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If fins are cut separately before gate formation, then fin cutting can be performed, but the process complexity increases and strain relaxation occurs

Engineering Contradiction:
Improvefin cutting processVSAvoidmanufacturing process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines the fin cutting operation with the gate etch process into a single step. The gate etch pattern is designed to simultaneously define both the gate structure and the fin cut locations, eliminating the need for a separate fin cutting step and reducing overall process complexity

Inventive Principle:
Principle #5Merging (Combining)

2Manufacturing precision

If fins are cut separately before gate formation, then fin cutting can be performed, but uniformity and electrical properties deteriorate due to strain relaxation

Engineering Contradiction:
Improvefin uniformityVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The replacement gate oxide is deposited over the fins before the gate etch step, serving as a protective layer that prevents strain relaxation during the cutting process. This preliminary action maintains fin uniformity and electrical properties while enabling the combined cutting and gating operation

Inventive Principle:
Principle #10Preliminary action

3Productivity

If multiple separate steps are used for fin cutting and gate formation, then each step can be optimized, but the overall manufacturing time increases

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidfin cut precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The gate etch pattern is designed to simultaneously define both the gate structure and the fin cut locations, eliminating the need for a separate fin cutting step and reducing overall process complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The replacement gate oxide serves as an intermediary protective layer during the combined gate etch and fin cutting step, enabling precise fin cutting while maintaining fin integrity and electrical properties

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for more uniform fin formation and improved electrical properties by cutting fins during the gate etch process, eliminating the need for separate fin cutting and reducing the complexity of the manufacturing process.

Implementation Method 1

removing the oxide from the exposed portion of the plurality of fins

Methodology Applied
Scientific EffectChemical etching:

Implementation Method 2

etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer

Methodology Applied
Scientific EffectReactive ion etching:

Data Source

PatentUS10242981B2Fin cut during replacement gate formation
Publication Date: 2019.03.26 ADEIA SEMICONDUCTOR SOLUTIONS LLC
  • US10242981B2 patent drawing
  • US10242981B2 patent drawing
  • US10242981B2 patent drawing

AI summary

A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.