Fin Cutting Strain Retention via Liner and Dielectric Fill

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Solution Overview

Problem

Strain in semiconductor devices can relax undesirably when fins are cut, leading to performance degradation and shorting of source/drain regions during epitaxial growth, which affects the reliability and efficiency of semiconductor devices.

Innovation Solution

The method involves forming a sacrificial gate and spacers on fins, followed by selective etching to create cavities that allow for the deposition of a liner layer and dielectric fill material, which helps maintain strain on the fins and prevent shorting of source/drain regions by controlling the growth process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If fins are cut during device fabrication, then device complexity is reduced and manufacturing is simplified, but strain in the channel region relaxes and source/drain regions may short

Engineering Contradiction:
Improvefin structure complexityVSAvoidstrain maintenance and source/drain isolation
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

A liner layer is deposited on the fin surface before the fin is cut. This preliminary deposition ensures that when the fin is subsequently cut, the liner layer remains intact and prevents strain relaxation and source/drain shorting at the cut surface

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The liner layer acts as an intermediary material between the fin structure and the external environment. It mediates the mechanical stress at the cut surface, preventing strain relaxation while also electrically isolating the source and drain regions

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If epitaxial growth is performed without proper fin protection, then source/drain regions can grow together and short, but adding protection layers increases process complexity

Engineering Contradiction:
Improvesource/drain region isolationVSAvoidepitaxial growth process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The liner layer is deposited on the fin surface before the epitaxial growth process begins. This preliminary protection ensures that the source and drain regions remain isolated during epitaxial growth without requiring complex in-process protection measures

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The liner layer serves as a sacrificial protection layer that is deposited, provides protection during epitaxial growth, and then can be selectively removed. This disposable protection layer simplifies the overall process compared to complex reusable protection systems

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively maintains strain on the fins during cutting and reduces the likelihood of source/drain region shorting, enhancing the performance and reliability of semiconductor devices by preserving the desired strain characteristics.

Implementation Method 1

Portions of the sacrificial liner layer and portions of a gate cap are removed to expose portions of the sacrificial gate

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

A liner layer is deposited in the first cavity and the second cavity

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Implementation Method 3

A dielectric fill material is deposited in the first and second cavity

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Implementation Method 4

forming spacers adjacent to sidewalls of the sacrificial gate

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS9721848B1Cutting fins and gates in CMOS devices
Publication Date: 2017.08.01 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9721848B1 patent drawing
  • US9721848B1 patent drawing
  • US9721848B1 patent drawing

AI summary

A semiconductor device includes a first fin and a second fin arranged on a substrate, a gate stack arranged over a channel region of the first fin, and spacers arranged along sidewalls of the gate stack. A cavity is arranged adjacent to a distal end of the gate stack. The cavity is defined by the substrate, a distal end of the second fin, and the spacers. A dielectric fill material is arranged in the cavity such that the dielectric fill material contacts the substrate, the distal end of the second fin, and the spacers.